drm/i915/gt: Suppress unclaimed mmio warnings for irq enabling
diff mbox series

Message ID 20191208233456.3074345-1-chris@chris-wilson.co.uk
State New
Headers show
Series
  • drm/i915/gt: Suppress unclaimed mmio warnings for irq enabling
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Commit Message

Chris Wilson Dec. 8, 2019, 11:34 p.m. UTC
Despite taking the intel_gt wakeref, and asserting that we do indeed
hold the runtime-pm wakeref for the device, our mmio debug insists that
the irq enabling is not being recognised:

[   19.342117] Unclaimed write to register 0x220a8
[   19.342185] WARNING: CPU: 2 PID: 619 at __unclaimed_reg_debug+0x4f/0x60 [i915]
[   19.342192] Modules linked in: nls_ascii nls_cp437 vfat i915 crct10dif_pclmul fat crc32_pclmul crc32c_intel aesni_intel glue_helper crypto_simd cryptd intel_cstate ahci intel_gtt libahci intel_uncore drm_kms_helper intel_rapl_perf i2c_i801 efivars video button efivarfs
[   19.342224] CPU: 2 PID: 619 Comm: gem_exec_parse_ Tainted: G     U            5.4.0-rc8+ #389
[   19.342230] Hardware name: Intel Corporation NUC7i5BNK/NUC7i5BNB, BIOS BNKBL357.86A.0052.2017.0918.1346 09/18/2017
[   19.342283] RIP: 0010:__unclaimed_reg_debug+0x4f/0x60 [i915]
[   19.342291] Code: 06 5b 5d 41 5c c3 c3 45 84 e4 48 c7 c0 15 af 2c a0 48 c7 c6 0b af 2c a0 89 ea 48 0f 44 f0 48 c7 c7 1e af 2c a0 e8 c7 56 e9 e0 <0f> 0b 83 2d e8 03 18 00 01 5b 5d 41 5c c3 0f 1f 00 23 b7 a4 00 00
[   19.342301] RSP: 0018:ffffc90000553a28 EFLAGS: 00010092
[   19.342309] RAX: 0000000000000023 RBX: 0000000000000000 RCX: 0000000000000006
[   19.342316] RDX: 0000000000000007 RSI: 0000000000000086 RDI: ffff88885eb163a0
[   19.342322] RBP: 00000000000220a8 R08: 000000000000028c R09: ffff88885a4c47c0
[   19.342328] R10: 0000000000000000 R11: 000000085488de02 R12: 0000000000000000
[   19.342334] R13: ffff8888548407c8 R14: 0000000000000006 R15: ffffc90000553b7c
[   19.342341] FS:  00007f0e8a2879c0(0000) GS:ffff88885eb00000(0000) knlGS:0000000000000000
[   19.342349] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   19.342355] CR2: 00007f0e8c235e12 CR3: 0000000858ef7001 CR4: 00000000001606e0
[   19.342361] Call Trace:
[   19.342413]  fwtable_write32+0x1a0/0x1e0 [i915]
[   19.342476]  gen8_logical_ring_enable_irq+0x2d/0x40 [i915]
[   19.342541]  irq_enable.part.14+0x1d/0x30 [i915]
[   19.342598]  i915_request_enable_breadcrumb+0x16a/0x1a0 [i915]
[   19.342611]  ? sync_file_alloc+0x80/0x80
[   19.342620]  __dma_fence_enable_signaling+0x2c/0x50
[   19.342629]  dma_fence_add_callback+0x34/0x90
[   19.342638]  sync_file_poll+0x7b/0xa0

Just silence the critics :(

References: 045d1fb79616 ("drm/i915/gt: Acquire a GT wakeref for the breadcrumb interrupt")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

Comments

Chris Wilson Dec. 9, 2019, 1:54 a.m. UTC | #1
Quoting Chris Wilson (2019-12-08 23:34:56)
> Despite taking the intel_gt wakeref, and asserting that we do indeed
> hold the runtime-pm wakeref for the device, our mmio debug insists that
> the irq enabling is not being recognised:

Scratch the dropping of fw, we miss interrupts.
-Chris

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index fcd9bb771223..0bfafc29a3dc 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3338,14 +3338,16 @@  static int gen9_emit_bb_start(struct i915_request *rq,
 
 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
 {
-	ENGINE_WRITE(engine, RING_IMR,
-		     ~(engine->irq_enable_mask | engine->irq_keep_mask));
+	GEM_BUG_ON(!intel_gt_pm_is_awake(engine->gt));
+
+	ENGINE_WRITE_FW(engine, RING_IMR,
+			~(engine->irq_enable_mask | engine->irq_keep_mask));
 	ENGINE_POSTING_READ(engine, RING_IMR);
 }
 
 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
 {
-	ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
+	ENGINE_WRITE_FW(engine, RING_IMR, ~engine->irq_keep_mask);
 }
 
 static int gen8_emit_flush(struct i915_request *request, u32 mode)