[v4,14/15] drm/i915/dsi: Fix state mismatch warns for horizontal timings with DSC
diff mbox series

Message ID c00f21965dce5572756dcc1ecda04a7e2e76a027.1575907078.git.jani.nikula@intel.com
State New
Headers show
Series
  • drm/i915/dsi: enable DSC
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Commit Message

Jani Nikula Dec. 9, 2019, 4:02 p.m. UTC
From: Vandita Kulkarni <vandita.kulkarni@intel.com>

When DSC is enabled consider the compression ratio that was used during
horizontal timing calculations.

This may still lead to warns due to rounding errors in the round-trip.

v2 by Jani:
- rebase on top of the more generic dsc state readout

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index caa477c4b1af..b1d775d834d4 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1255,6 +1255,18 @@  static void gen11_dsi_get_timings(struct intel_encoder *encoder,
 	struct drm_display_mode *adjusted_mode =
 					&pipe_config->hw.adjusted_mode;
 
+	if (pipe_config->dsc.compressed_bpp) {
+		int div = pipe_config->dsc.compressed_bpp;
+		int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+
+		adjusted_mode->crtc_htotal =
+			DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
+		adjusted_mode->crtc_hsync_start =
+			DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
+		adjusted_mode->crtc_hsync_end =
+			DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
+	}
+
 	if (intel_dsi->dual_link) {
 		adjusted_mode->crtc_hdisplay *= 2;
 		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)