@@ -6876,6 +6876,17 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
} else {
u32 pp_ctl;
+ /*
+ * Display WA #1124: bxt,glk,cnl
+ * "WA: Wait at least 100us between programming
+ * PP_ON_DELAYS and enabling Power State Target in
+ * PP_CONTROL, or disable dpls clock gating before
+ * programming PP_ON_DELAYS and leave disabled until
+ * after enabling Power State Target in PP_CONTROL."
+ */
+ if (INTEL_GEN(dev_priv) < 11)
+ usleep_range(100, 200);
+
pp_ctl = I915_READ(regs.pp_ctrl);
pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));