From patchwork Tue Dec 10 14:41:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11282691 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 798E114BD for ; Tue, 10 Dec 2019 14:48:25 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 619AB20637 for ; Tue, 10 Dec 2019 14:48:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 619AB20637 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 05AF66E8F6; Tue, 10 Dec 2019 14:48:25 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 401FF6E8F6 for ; Tue, 10 Dec 2019 14:48:23 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Dec 2019 06:41:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,300,1571727600"; d="scan'208";a="210413356" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga007.fm.intel.com with SMTP; 10 Dec 2019 06:41:13 -0800 Received: by stinkbox (sSMTP sendmail emulation); Tue, 10 Dec 2019 16:41:13 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 10 Dec 2019 16:41:03 +0200 Message-Id: <20191210144105.3239-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191210144105.3239-1-ville.syrjala@linux.intel.com> References: <20191210144105.3239-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 2/4] drm/i915: Polish WM_LINETIME register stuff X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Let's store the normal and IPS linetime watermarks individually, and while at it we'll pimp the register definitions as well. v2: Deal with gvt Reviewed-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä --- .../drm/i915/display/intel_display_types.h | 3 +- drivers/gpu/drm/i915/gvt/handlers.c | 6 +- drivers/gpu/drm/i915/i915_reg.h | 14 ++-- drivers/gpu/drm/i915/intel_pm.c | 72 ++++++++++--------- 4 files changed, 52 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 83ea04149b77..f77f47efb8b6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -659,7 +659,8 @@ struct intel_crtc_scaler_state { struct intel_pipe_wm { struct intel_wm_level wm[5]; - u32 linetime; + u16 linetime; + u16 ips_linetime; bool fbc_wm_enabled; bool pipe_enabled; bool sprites_enabled; diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index bb9fe6bf5275..717c9afd9f6f 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -2401,9 +2401,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); - MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); - MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); - MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); + MMIO_D(WM_LINETIME(PIPE_A), D_ALL); + MMIO_D(WM_LINETIME(PIPE_B), D_ALL); + MMIO_D(WM_LINETIME(PIPE_C), D_ALL); MMIO_D(SPLL_CTL, D_ALL); MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL); MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1a6376a97d48..d20d42980d5c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10538,13 +10538,13 @@ enum skl_power_gate { #define D_COMP_COMP_DISABLE (1 << 0) /* Pipe WM_LINETIME - watermark line time */ -#define _PIPE_WM_LINETIME_A 0x45270 -#define _PIPE_WM_LINETIME_B 0x45274 -#define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B) -#define PIPE_WM_LINETIME_MASK (0x1ff) -#define PIPE_WM_LINETIME_TIME(x) ((x)) -#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff << 16) -#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x) << 16) +#define _WM_LINETIME_A 0x45270 +#define _WM_LINETIME_B 0x45274 +#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) +#define HSW_LINETIME_MASK REG_GENMASK(8, 0) +#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) +#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) +#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) /* SFUSE_STRAP */ #define SFUSE_STRAP _MMIO(0xc2014) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ccbbdf4a6aab..b9eb0a89be93 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2788,31 +2788,31 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, } static u32 -hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state) +hsw_linetime_wm(const struct intel_crtc_state *crtc_state) { - const struct intel_atomic_state *intel_state = + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + + if (!crtc_state->hw.active) + return 0; + + return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, + adjusted_mode->crtc_clock); +} + +static u32 +hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state) +{ + const struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - u32 linetime, ips_linetime; if (!crtc_state->hw.active) return 0; - if (WARN_ON(adjusted_mode->crtc_clock == 0)) - return 0; - if (WARN_ON(intel_state->cdclk.logical.cdclk == 0)) - return 0; - /* The WM are computed with base on how long it takes to fill a single - * row at the given clock rate, multiplied by 8. - * */ - linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, - adjusted_mode->crtc_clock); - ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, - intel_state->cdclk.logical.cdclk); - - return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | - PIPE_WM_LINETIME_TIME(linetime); + return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, + state->cdclk.logical.cdclk); } static void intel_read_wm_latency(struct drm_i915_private *dev_priv, @@ -3150,8 +3150,10 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state) ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state, pristate, sprstate, curstate, &pipe_wm->wm[0]); - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - pipe_wm->linetime = hsw_compute_linetime_wm(crtc_state); + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { + pipe_wm->linetime = hsw_linetime_wm(crtc_state); + pipe_wm->ips_linetime = hsw_ips_linetime_wm(crtc_state); + } if (!ilk_validate_pipe_wm(dev_priv, pipe_wm)) return -EINVAL; @@ -3351,7 +3353,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, enum intel_ddb_partitioning partitioning, struct ilk_wm_values *results) { - struct intel_crtc *intel_crtc; + struct intel_crtc *crtc; int level, wm_lp; results->enable_fbc_wm = merged->fbc_wm_enabled; @@ -3396,15 +3398,17 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, } /* LP0 register values */ - for_each_intel_crtc(&dev_priv->drm, intel_crtc) { - enum pipe pipe = intel_crtc->pipe; - const struct intel_wm_level *r = - &intel_crtc->wm.active.ilk.wm[0]; + for_each_intel_crtc(&dev_priv->drm, crtc) { + enum pipe pipe = crtc->pipe; + const struct intel_pipe_wm *pipe_wm = &crtc->wm.active.ilk; + const struct intel_wm_level *r = &pipe_wm->wm[0]; if (WARN_ON(!r->enable)) continue; - results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime; + results->wm_linetime[pipe] = + HSW_LINETIME(pipe_wm->linetime) | + HSW_IPS_LINETIME(pipe_wm->ips_linetime); results->wm_pipe[pipe] = (r->pri_val << WM0_PIPE_PLANE_SHIFT) | @@ -3557,11 +3561,11 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv, I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); if (dirty & WM_DIRTY_LINETIME(PIPE_A)) - I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); + I915_WRITE(WM_LINETIME(PIPE_A), results->wm_linetime[0]); if (dirty & WM_DIRTY_LINETIME(PIPE_B)) - I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); + I915_WRITE(WM_LINETIME(PIPE_B), results->wm_linetime[1]); if (dirty & WM_DIRTY_LINETIME(PIPE_C)) - I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); + I915_WRITE(WM_LINETIME(PIPE_C), results->wm_linetime[2]); if (dirty & WM_DIRTY_DDB) { if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { @@ -5532,7 +5536,7 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state, if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0) return; - I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime); + I915_WRITE(WM_LINETIME(pipe), HSW_LINETIME(pipe_wm->linetime)); } static void skl_initial_wm(struct intel_atomic_state *state, @@ -5677,7 +5681,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, if (!crtc->active) return; - out->linetime = I915_READ(PIPE_WM_LINETIME(pipe)); + val = I915_READ(WM_LINETIME(pipe)); + out->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, val); } void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) @@ -5719,7 +5724,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc) hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); + hw->wm_linetime[pipe] = I915_READ(WM_LINETIME(pipe)); memset(active, 0, sizeof(*active)); @@ -5738,7 +5743,10 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc) active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; - active->linetime = hw->wm_linetime[pipe]; + active->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, + hw->wm_linetime[pipe]); + active->ips_linetime = REG_FIELD_GET(HSW_IPS_LINETIME_MASK, + hw->wm_linetime[pipe]); } else { int level, max_level = ilk_wm_max_level(dev_priv);