drm/i915: Add DPCD quirk for AUO PSR2 panel
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Message ID 1575994399-15799-1-git-send-email-gaurav.k.singh@intel.com
State New
Headers show
Series
  • drm/i915: Add DPCD quirk for AUO PSR2 panel
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Commit Message

Gaurav K Singh Dec. 10, 2019, 4:13 p.m. UTC
Currently on AUO PSR2 panel on Gen9 chromebook, we are observing
below issues:
(i) The display will show garbage after pressing sign
out icon in log in screen when wallpaper is one of Solid colors
& PSR2 is enabled
(ii) The characters of display is not clear when switch
OS mode to dev mode.

Before this patch, on this panel, we set idle frame count to 6
that is number of idle frames before entering PSR2 deep sleep
and the number of frames to enter into Selective update we set
to 1.

On this AUO panel, we suspect there is some DP synchronization
latency needed, due to which we are facing the above issues.

With current TCON of the AUO panel, DPCD reg
DP_SYNCHRONIZATION_LATENCY_IN_SINK (0x2009) offset is giving a
value of 0x0.

This patch sets idle frame count to 9 and frame count for selective
update to 9, after which we are not seeing the above mentioned issues.

Ideally this value needs to be corrected in TCON of the panel
since this value comes from DPCD reg 0x2009 offset and i915 driver
uses it. Working with AUO panel vendor to get this fixed in the
panel TCON. In the meantime fixing this as DPCD quirk in the kernel.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c          | 3 +++
 drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
 include/drm/drm_dp_helper.h              | 9 +++++++++
 3 files changed, 18 insertions(+)

Comments

kbuild test robot Dec. 11, 2019, 12:47 a.m. UTC | #1
Hi Gaurav,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip linus/master v5.5-rc1 next-20191210]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Gaurav-K-Singh/drm-i915-Add-DPCD-quirk-for-AUO-PSR2-panel/20191211-064743
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce: make htmldocs

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

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   include/drm/drm_dp_helper.h:1525: warning: Incorrect use of kernel-doc format:          * @DP_DPCD_QUIRK_SYNCHRONIZATION_LATENCY
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vim +1533 include/drm/drm_dp_helper.h

118b90f3f18e73 Jani Nikula           2017-05-18  1490  
118b90f3f18e73 Jani Nikula           2017-05-18  1491  int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
118b90f3f18e73 Jani Nikula           2017-05-18  1492  		     bool is_branch);
118b90f3f18e73 Jani Nikula           2017-05-18  1493  
76fa998acd86b6 Jani Nikula           2017-05-18  1494  /**
76fa998acd86b6 Jani Nikula           2017-05-18  1495   * enum drm_dp_quirk - Display Port sink/branch device specific quirks
76fa998acd86b6 Jani Nikula           2017-05-18  1496   *
76fa998acd86b6 Jani Nikula           2017-05-18  1497   * Display Port sink and branch devices in the wild have a variety of bugs, try
76fa998acd86b6 Jani Nikula           2017-05-18  1498   * to collect them here. The quirks are shared, but it's up to the drivers to
76fa998acd86b6 Jani Nikula           2017-05-18  1499   * implement workarounds for them.
76fa998acd86b6 Jani Nikula           2017-05-18  1500   */
76fa998acd86b6 Jani Nikula           2017-05-18  1501  enum drm_dp_quirk {
76fa998acd86b6 Jani Nikula           2017-05-18  1502  	/**
53ca2edcf033f3 Lee, Shawn C          2018-09-11  1503  	 * @DP_DPCD_QUIRK_CONSTANT_N:
76fa998acd86b6 Jani Nikula           2017-05-18  1504  	 *
76fa998acd86b6 Jani Nikula           2017-05-18  1505  	 * The device requires main link attributes Mvid and Nvid to be limited
53ca2edcf033f3 Lee, Shawn C          2018-09-11  1506  	 * to 16 bits. So will give a constant value (0x8000) for compatability.
76fa998acd86b6 Jani Nikula           2017-05-18  1507  	 */
53ca2edcf033f3 Lee, Shawn C          2018-09-11  1508  	DP_DPCD_QUIRK_CONSTANT_N,
7c5c641a930ed0 José Roberto de Souza 2018-12-03  1509  	/**
ed17b555303c74 José Roberto de Souza 2018-12-05  1510  	 * @DP_DPCD_QUIRK_NO_PSR:
7c5c641a930ed0 José Roberto de Souza 2018-12-03  1511  	 *
7c5c641a930ed0 José Roberto de Souza 2018-12-03  1512  	 * The device does not support PSR even if reports that it supports or
7c5c641a930ed0 José Roberto de Souza 2018-12-03  1513  	 * driver still need to implement proper handling for such device.
7c5c641a930ed0 José Roberto de Souza 2018-12-03  1514  	 */
7c5c641a930ed0 José Roberto de Souza 2018-12-03  1515  	DP_DPCD_QUIRK_NO_PSR,
7974033e527a5d Ville Syrjälä         2019-05-28  1516  	/**
7974033e527a5d Ville Syrjälä         2019-05-28  1517  	 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
7974033e527a5d Ville Syrjälä         2019-05-28  1518  	 *
7974033e527a5d Ville Syrjälä         2019-05-28  1519  	 * The device does not set SINK_COUNT to a non-zero value.
7974033e527a5d Ville Syrjälä         2019-05-28  1520  	 * The driver should ignore SINK_COUNT during detection.
7974033e527a5d Ville Syrjälä         2019-05-28  1521  	 */
7974033e527a5d Ville Syrjälä         2019-05-28  1522  	DP_DPCD_QUIRK_NO_SINK_COUNT,
8c57c0a07182ad Gaurav K Singh        2019-12-10  1523  	/**
8c57c0a07182ad Gaurav K Singh        2019-12-10  1524  	 * @DP_DPCD_QUIRK_SYNCHRONIZATION_LATENCY
8c57c0a07182ad Gaurav K Singh        2019-12-10 @1525  	 *
8c57c0a07182ad Gaurav K Singh        2019-12-10  1526  	 * The Helios AUO PSR2 panel requires more number of frames on PSR exit,
8c57c0a07182ad Gaurav K Singh        2019-12-10  1527  	 * to synchronize to the Source device-provided timing. Currently DPCD
8c57c0a07182ad Gaurav K Singh        2019-12-10  1528  	 * 0x2009 offset in TCON has the value of 0. Increasing this value to 8
8c57c0a07182ad Gaurav K Singh        2019-12-10  1529  	 * till this gets fixed in TCON of the panel.
8c57c0a07182ad Gaurav K Singh        2019-12-10  1530  	 */
8c57c0a07182ad Gaurav K Singh        2019-12-10  1531  	DP_DPCD_QUIRK_SYNCHRONIZATION_LATENCY,
76fa998acd86b6 Jani Nikula           2017-05-18  1532  };
76fa998acd86b6 Jani Nikula           2017-05-18 @1533  

:::::: The code at line 1533 was first introduced by commit
:::::: 76fa998acd86b6b40d0217e12af39c2406bdcd2b drm/dp: start a DPCD based DP sink/branch device quirk database

:::::: TO: Jani Nikula <jani.nikula@intel.com>
:::::: CC: Jani Nikula <jani.nikula@intel.com>

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation
Jani Nikula Jan. 2, 2020, 10:01 a.m. UTC | #2
On Tue, 10 Dec 2019, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> Currently on AUO PSR2 panel on Gen9 chromebook, we are observing
> below issues:
> (i) The display will show garbage after pressing sign
> out icon in log in screen when wallpaper is one of Solid colors
> & PSR2 is enabled
> (ii) The characters of display is not clear when switch
> OS mode to dev mode.
>
> Before this patch, on this panel, we set idle frame count to 6
> that is number of idle frames before entering PSR2 deep sleep
> and the number of frames to enter into Selective update we set
> to 1.
>
> On this AUO panel, we suspect there is some DP synchronization
> latency needed, due to which we are facing the above issues.
>
> With current TCON of the AUO panel, DPCD reg
> DP_SYNCHRONIZATION_LATENCY_IN_SINK (0x2009) offset is giving a
> value of 0x0.
>
> This patch sets idle frame count to 9 and frame count for selective
> update to 9, after which we are not seeing the above mentioned issues.
>
> Ideally this value needs to be corrected in TCON of the panel
> since this value comes from DPCD reg 0x2009 offset and i915 driver
> uses it. Working with AUO panel vendor to get this fixed in the
> panel TCON. In the meantime fixing this as DPCD quirk in the kernel.
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c          | 3 +++
>  drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
>  include/drm/drm_dp_helper.h              | 9 +++++++++
>  3 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 2c7870aef469..96eaeef814d3 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1155,6 +1155,9 @@ struct dpcd_quirk {
>  	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
>  	/* CH7511 seems to leave SINK_COUNT zeroed */
>  	{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
> +	/* AUO PSR2 panels need some more DP synchronization latency */
> +	{ OUI(0x00, 0x1c, 0xf8), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_SYNCHRONIZATION_LATENCY) },

DEVICE_ID_ANY seems pretty lax.

BR,
Jani.

> +
>  };
>  
>  #undef OUI
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 16e9ff47d519..1023b08ad093 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -296,6 +296,12 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>  	dev_priv->psr.sink_sync_latency =
>  		intel_dp_get_sink_sync_latency(intel_dp);
>  
> +	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_SYNCHRONIZATION_LATENCY)) {
> +		DRM_DEBUG_KMS("AUO PSR2 panel need more synchronization latency\n");
> +		if (dev_priv->psr.sink_sync_latency == 0)
> +			dev_priv->psr.sink_sync_latency = 8;
> +	}
> +
>  	dev_priv->psr.dp = intel_dp;
>  
>  	if (INTEL_GEN(dev_priv) >= 9 &&
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 8f8f3632e697..6018b79f2d61 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1522,6 +1522,15 @@ enum drm_dp_quirk {
>  	 * The driver should ignore SINK_COUNT during detection.
>  	 */
>  	DP_DPCD_QUIRK_NO_SINK_COUNT,
> +	/**
> +	 * @DP_DPCD_QUIRK_SYNCHRONIZATION_LATENCY
> +	 *
> +	 * The Helios AUO PSR2 panel requires more number of frames on PSR exit,
> +	 * to synchronize to the Source device-provided timing. Currently DPCD
> +	 * 0x2009 offset in TCON has the value of 0. Increasing this value to 8
> +	 * till this gets fixed in TCON of the panel.
> +	 */
> +	DP_DPCD_QUIRK_SYNCHRONIZATION_LATENCY,
>  };
>  
>  /**

Patch
diff mbox series

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 2c7870aef469..96eaeef814d3 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1155,6 +1155,9 @@  struct dpcd_quirk {
 	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
 	/* CH7511 seems to leave SINK_COUNT zeroed */
 	{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
+	/* AUO PSR2 panels need some more DP synchronization latency */
+	{ OUI(0x00, 0x1c, 0xf8), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_SYNCHRONIZATION_LATENCY) },
+
 };
 
 #undef OUI
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 16e9ff47d519..1023b08ad093 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -296,6 +296,12 @@  void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 	dev_priv->psr.sink_sync_latency =
 		intel_dp_get_sink_sync_latency(intel_dp);
 
+	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_SYNCHRONIZATION_LATENCY)) {
+		DRM_DEBUG_KMS("AUO PSR2 panel need more synchronization latency\n");
+		if (dev_priv->psr.sink_sync_latency == 0)
+			dev_priv->psr.sink_sync_latency = 8;
+	}
+
 	dev_priv->psr.dp = intel_dp;
 
 	if (INTEL_GEN(dev_priv) >= 9 &&
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 8f8f3632e697..6018b79f2d61 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1522,6 +1522,15 @@  enum drm_dp_quirk {
 	 * The driver should ignore SINK_COUNT during detection.
 	 */
 	DP_DPCD_QUIRK_NO_SINK_COUNT,
+	/**
+	 * @DP_DPCD_QUIRK_SYNCHRONIZATION_LATENCY
+	 *
+	 * The Helios AUO PSR2 panel requires more number of frames on PSR exit,
+	 * to synchronize to the Source device-provided timing. Currently DPCD
+	 * 0x2009 offset in TCON has the value of 0. Increasing this value to 8
+	 * till this gets fixed in TCON of the panel.
+	 */
+	DP_DPCD_QUIRK_SYNCHRONIZATION_LATENCY,
 };
 
 /**