@@ -1346,6 +1346,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
"snps,dis-del-phy-power-chg-quirk");
dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
"snps,dis-tx-ipgap-linecheck-quirk");
+ dwc->dis_mult_trb_fetch = device_property_read_bool(dev,
+ "snps,dis-mult-trb-fetch");
dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
"snps,tx_de_emphasis_quirk");
@@ -146,6 +146,7 @@
#define DWC3_DSTS 0xc70c
#define DWC3_DGCMDPAR 0xc710
#define DWC3_DGCMD 0xc714
+#define DWC32_DCTL1 0xc718 /* DWC_usb32 only */
#define DWC3_DALEPENA 0xc720
#define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
@@ -441,6 +442,8 @@
#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
+#define DWC32_DCTL1_SINGLE_TRB_FETCH BIT(0)
+
/* Device Event Enable Register */
#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
#define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
@@ -1040,6 +1043,7 @@ struct dwc3_scratchpad_array {
* change quirk.
* @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
* check during HS transmit.
+ * @dis_mult_trb_fetch: set to disable multiple TRB cache
* @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
* @tx_de_emphasis: Tx de-emphasis value
* 0 - -6dB de-emphasis
@@ -1229,6 +1233,7 @@ struct dwc3 {
unsigned dis_u2_freeclk_exists_quirk:1;
unsigned dis_del_phy_power_chg_quirk:1;
unsigned dis_tx_ipgap_linecheck_quirk:1;
+ unsigned dis_mult_trb_fetch:1;
unsigned tx_de_emphasis_quirk:1;
unsigned tx_de_emphasis:2;
@@ -3506,6 +3506,18 @@ int dwc3_gadget_init(struct dwc3 *dwc)
goto err4;
}
+ if (dwc3_is_usb32(dwc) && dwc->dis_mult_trb_fetch) {
+ u32 reg;
+
+ /*
+ * For optimal performance, set DCTL1.SINGLE_TRB_FETCH_EN
+ * if the number of trb prefetch is 2 or less.
+ */
+ reg = dwc3_readl(dwc->regs, DWC32_DCTL1);
+ reg |= DWC32_DCTL1_SINGLE_TRB_FETCH;
+ dwc3_writel(dwc->regs, DWC32_DCTL1, reg);
+ }
+
if (dwc3_is_usb32(dwc) && dwc->maximum_lsm)
dwc3_gadget_set_sublink_attr(&dwc->gadget,
dwc->maximum_lanes,
DWC_usb32 controller allows the HW to send multiple TRB fetch requests. If the second fetch to the same TRB complete before the previous request, then the result of the second fetch is taken and the first to drop. This feature improve the performance when the number of cache TRB is greater than 2. DWC_usb32 also has the option to issue only single TRB fetch, which this patch implements the "snps,dis-mult-trb-fetch" property. For optimal performance, the programming guide recommend to do only single TRB fetch if num_trb_prefetch is 2 or lower. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> --- drivers/usb/dwc3/core.c | 2 ++ drivers/usb/dwc3/core.h | 5 +++++ drivers/usb/dwc3/gadget.c | 12 ++++++++++++ 3 files changed, 19 insertions(+)