arm64: dts: mt8173: add Mediatek JPEG Codec
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Message ID 20191213045720.172738-1-hsinyi@chromium.org
State New
Headers show
Series
  • arm64: dts: mt8173: add Mediatek JPEG Codec
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Commit Message

Hsin-Yi Wang Dec. 13, 2019, 4:57 a.m. UTC
Add JPEG codec node in mt8173.

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

Comments

Matthias Brugger Dec. 14, 2019, 9:40 p.m. UTC | #1
On 13/12/2019 05:57, Hsin-Yi Wang wrote:
> Add JPEG codec node in mt8173.
> 
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> ---

Applied to v5.5-next/dts64

Thanks!

>  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 15f1842f6df3..82df8940d515 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -1401,6 +1401,20 @@ vcodec_enc: vcodec@18002000 {
>  						 <&topckgen CLK_TOP_UNIVPLL1_D2>;
>  		};
>  
> +		jpegdec: jpegdec@18004000 {
> +			compatible = "mediatek,mt8173-jpgdec";
> +			reg = <0 0x18004000 0 0x1000>;
> +			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&vencsys CLK_VENC_CKE0>,
> +				 <&vencsys CLK_VENC_CKE3>;
> +			clock-names = "jpgdec-smi",
> +				      "jpgdec";
> +			power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
> +			mediatek,larb = <&larb3>;
> +			iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
> +				 <&iommu M4U_PORT_JPGDEC_BSDMA>;
> +		};
> +
>  		vencltsys: clock-controller@19000000 {
>  			compatible = "mediatek,mt8173-vencltsys", "syscon";
>  			reg = <0 0x19000000 0 0x1000>;
>

Patch
diff mbox series

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 15f1842f6df3..82df8940d515 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1401,6 +1401,20 @@  vcodec_enc: vcodec@18002000 {
 						 <&topckgen CLK_TOP_UNIVPLL1_D2>;
 		};
 
+		jpegdec: jpegdec@18004000 {
+			compatible = "mediatek,mt8173-jpgdec";
+			reg = <0 0x18004000 0 0x1000>;
+			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&vencsys CLK_VENC_CKE0>,
+				 <&vencsys CLK_VENC_CKE3>;
+			clock-names = "jpgdec-smi",
+				      "jpgdec";
+			power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
+			mediatek,larb = <&larb3>;
+			iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
+				 <&iommu M4U_PORT_JPGDEC_BSDMA>;
+		};
+
 		vencltsys: clock-controller@19000000 {
 			compatible = "mediatek,mt8173-vencltsys", "syscon";
 			reg = <0 0x19000000 0 0x1000>;