drm/i915: Fix WARN_ON condition for cursor plane ddb allocation
diff mbox series

Message ID 20191213154515.12121-1-vandita.kulkarni@intel.com
State New
Headers show
Series
  • drm/i915: Fix WARN_ON condition for cursor plane ddb allocation
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Commit Message

Vandita Kulkarni Dec. 13, 2019, 3:45 p.m. UTC
In some cases min_ddb_alloc can be U16_MAX, exclude it
from the WARN_ON.

Fixes: 10a7e07b68b9 ("drm/i915: Make sure cursor has enough ddb for the selected wm level")
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Ville Syrjälä Dec. 13, 2019, 5:03 p.m. UTC | #1
On Fri, Dec 13, 2019 at 09:15:15PM +0530, Vandita Kulkarni wrote:
> In some cases min_ddb_alloc can be U16_MAX, exclude it
> from the WARN_ON.

The two cases I think are:
latency[level]==0 or wm[level].res_lines>31

You said you hit the latter case.

May want to mention those in the commit message.

> 
> Fixes: 10a7e07b68b9 ("drm/i915: Make sure cursor has enough ddb for the selected wm level")
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ccbbdf4a6aab..cec4fa79422c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4312,8 +4312,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  				&crtc_state->wm.skl.optimal.planes[plane_id];
>  
>  			if (plane_id == PLANE_CURSOR) {
> -				if (WARN_ON(wm->wm[level].min_ddb_alloc >
> -					    total[PLANE_CURSOR])) {
> +				if (wm->wm[level].min_ddb_alloc >
> +				    total[PLANE_CURSOR]) {
> +					WARN_ON(wm->wm[level].min_ddb_alloc !=
> +						U16_MAX);
>  					blocks = U32_MAX;

The line wraps make this look rather ugly. Might be better to just
ignore the 80col limit here.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  					break;
>  				}
> -- 
> 2.21.0.5.gaeb582a

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ccbbdf4a6aab..cec4fa79422c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4312,8 +4312,10 @@  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 				&crtc_state->wm.skl.optimal.planes[plane_id];
 
 			if (plane_id == PLANE_CURSOR) {
-				if (WARN_ON(wm->wm[level].min_ddb_alloc >
-					    total[PLANE_CURSOR])) {
+				if (wm->wm[level].min_ddb_alloc >
+				    total[PLANE_CURSOR]) {
+					WARN_ON(wm->wm[level].min_ddb_alloc !=
+						U16_MAX);
 					blocks = U32_MAX;
 					break;
 				}