[v2] clk: meson: pll: Fix by 0 division in __pll_params_to_rate()
diff mbox series

Message ID 20191215114705.24401-1-repk@triplefau.lt
State New, archived
Delegated to: Neil Armstrong
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Series
  • [v2] clk: meson: pll: Fix by 0 division in __pll_params_to_rate()
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Commit Message

Remi Pommarel Dec. 15, 2019, 11:47 a.m. UTC
Some meson pll registers can be initialized with 0 as N value, introducing
the following division by 0 when computing rate :

  UBSAN: Undefined behaviour in drivers/clk/meson/clk-pll.c:75:9
  division by zero
  CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc3-608075-g86c9af8630e1-dirty #400
  Call trace:
   dump_backtrace+0x0/0x1c0
   show_stack+0x14/0x20
   dump_stack+0xc4/0x100
   ubsan_epilogue+0x14/0x68
   __ubsan_handle_divrem_overflow+0x98/0xb8
   __pll_params_to_rate+0xdc/0x140
   meson_clk_pll_recalc_rate+0x278/0x3a0
   __clk_register+0x7c8/0xbb0
   devm_clk_hw_register+0x54/0xc0
   meson_eeclkc_probe+0xf4/0x1a0
   platform_drv_probe+0x54/0xd8
   really_probe+0x16c/0x438
   driver_probe_device+0xb0/0xf0
   device_driver_attach+0x94/0xa0
   __driver_attach+0x70/0x108
   bus_for_each_dev+0xd8/0x128
   driver_attach+0x30/0x40
   bus_add_driver+0x1b0/0x2d8
   driver_register+0xbc/0x1d0
   __platform_driver_register+0x78/0x88
   axg_driver_init+0x18/0x20
   do_one_initcall+0xc8/0x24c
   kernel_init_freeable+0x2b0/0x344
   kernel_init+0x10/0x128
   ret_from_fork+0x10/0x18

This checks if N is null before doing the division.

Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller")
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
---
Changes since v1:
  - Change Fix tag
  - Move null test to .recalc_rate()
---
 drivers/clk/meson/clk-pll.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Martin Blumenstingl Dec. 15, 2019, 8:34 p.m. UTC | #1
On Sun, Dec 15, 2019 at 12:39 PM Remi Pommarel <repk@triplefau.lt> wrote:
>
> Some meson pll registers can be initialized with 0 as N value, introducing
> the following division by 0 when computing rate :
>
>   UBSAN: Undefined behaviour in drivers/clk/meson/clk-pll.c:75:9
>   division by zero
>   CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc3-608075-g86c9af8630e1-dirty #400
>   Call trace:
>    dump_backtrace+0x0/0x1c0
>    show_stack+0x14/0x20
>    dump_stack+0xc4/0x100
>    ubsan_epilogue+0x14/0x68
>    __ubsan_handle_divrem_overflow+0x98/0xb8
>    __pll_params_to_rate+0xdc/0x140
>    meson_clk_pll_recalc_rate+0x278/0x3a0
>    __clk_register+0x7c8/0xbb0
>    devm_clk_hw_register+0x54/0xc0
>    meson_eeclkc_probe+0xf4/0x1a0
>    platform_drv_probe+0x54/0xd8
>    really_probe+0x16c/0x438
>    driver_probe_device+0xb0/0xf0
>    device_driver_attach+0x94/0xa0
>    __driver_attach+0x70/0x108
>    bus_for_each_dev+0xd8/0x128
>    driver_attach+0x30/0x40
>    bus_add_driver+0x1b0/0x2d8
>    driver_register+0xbc/0x1d0
>    __platform_driver_register+0x78/0x88
>    axg_driver_init+0x18/0x20
>    do_one_initcall+0xc8/0x24c
>    kernel_init_freeable+0x2b0/0x344
>    kernel_init+0x10/0x128
>    ret_from_fork+0x10/0x18
>
> This checks if N is null before doing the division.
>
> Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller")
> Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

thank you for the patch Remi!


Martin
Jerome Brunet Dec. 16, 2019, 11:21 a.m. UTC | #2
On Sun 15 Dec 2019 at 21:34, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:

> On Sun, Dec 15, 2019 at 12:39 PM Remi Pommarel <repk@triplefau.lt> wrote:
>>
>> Some meson pll registers can be initialized with 0 as N value, introducing
>> the following division by 0 when computing rate :
>>
>>   UBSAN: Undefined behaviour in drivers/clk/meson/clk-pll.c:75:9
>>   division by zero
>>   CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc3-608075-g86c9af8630e1-dirty #400
>>   Call trace:
>>    dump_backtrace+0x0/0x1c0
>>    show_stack+0x14/0x20
>>    dump_stack+0xc4/0x100
>>    ubsan_epilogue+0x14/0x68
>>    __ubsan_handle_divrem_overflow+0x98/0xb8
>>    __pll_params_to_rate+0xdc/0x140
>>    meson_clk_pll_recalc_rate+0x278/0x3a0
>>    __clk_register+0x7c8/0xbb0
>>    devm_clk_hw_register+0x54/0xc0
>>    meson_eeclkc_probe+0xf4/0x1a0
>>    platform_drv_probe+0x54/0xd8
>>    really_probe+0x16c/0x438
>>    driver_probe_device+0xb0/0xf0
>>    device_driver_attach+0x94/0xa0
>>    __driver_attach+0x70/0x108
>>    bus_for_each_dev+0xd8/0x128
>>    driver_attach+0x30/0x40
>>    bus_add_driver+0x1b0/0x2d8
>>    driver_register+0xbc/0x1d0
>>    __platform_driver_register+0x78/0x88
>>    axg_driver_init+0x18/0x20
>>    do_one_initcall+0xc8/0x24c
>>    kernel_init_freeable+0x2b0/0x344
>>    kernel_init+0x10/0x128
>>    ret_from_fork+0x10/0x18
>>
>> This checks if N is null before doing the division.
>>
>> Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller")
>> Signed-off-by: Remi Pommarel <repk@triplefau.lt>
> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Applied with a slightly more detailed comment.
Thx

>
> thank you for the patch Remi!
>
>
> Martin

Patch
diff mbox series

diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index ddb1e5634739..4d3a8003ca20 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -77,6 +77,10 @@  static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
 	unsigned int m, n, frac;
 
 	n = meson_parm_read(clk->map, &pll->n);
+	/* Some hw may have n set to 0 at init, avoid div by 0 in that case */
+	if (n == 0)
+		return 0;
+
 	m = meson_parm_read(clk->map, &pll->m);
 
 	frac = MESON_PARM_APPLICABLE(&pll->frac) ?