Message ID | 20191216110904.30815-1-peter.maydell@linaro.org (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Mon, 16 Dec 2019 at 11:09, Peter Maydell <peter.maydell@linaro.org> wrote: > > > First arm pullreq of 5.0! > > The following changes since commit 084a398bf8aa7634738e6c6c0103236ee1b3b72f: > > Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2019-12-13 18:14:07 +0000) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191216-1 > > for you to fetch changes up to f80741d107673f162e3b097fc76a1590036cc9d1: > > target/arm: ensure we use current exception state after SCR update (2019-12-16 10:52:58 +0000) > > ---------------------------------------------------------------- > target-arm queue: > * Add support for Cortex-M7 CPU > * exynos4210_gic: Suppress gcc9 format-truncation warnings > * aspeed: Various minor bug fixes and improvements > * aspeed: Add support for the tacoma-bmc board > * Honour HCR_EL32.TID1 and .TID2 trapping requirements > * Handle trapping to EL2 of AArch32 VMRS instructions > * Handle AArch32 CP15 trapping via HSTR_EL2 > * Add support for missing Jazelle system registers > * arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on > * Add support for DC CVAP & DC CVADP instructions > * Fix assertion when SCR.NS is changed in Secure-SVC &c > * enable SHPC native hot plug in arm ACPI > > ---------------------------------------------------------------- Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0 for any user-visible changes. -- PMM