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[4.19.y-cip,39/39] arm64: defconfig: Enable R8A774B1 SoC

Message ID	1576668829-59767-40-git-send-email-biju.das@bp.renesas.com (mailing list archive)
State	Accepted
Delegated to:	Chris Paterson
Headers	show Return-Path: <SRS0=rJJM=2I=lists.cip-project.org=cip-dev-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 301AB24676 From: Biju Das <biju.das@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Date: Wed, 18 Dec 2019 11:33:49 +0000 Message-Id: <1576668829-59767-40-git-send-email-biju.das@bp.renesas.com> In-Reply-To: <1576668829-59767-1-git-send-email-biju.das@bp.renesas.com> References: <1576668829-59767-1-git-send-email-biju.das@bp.renesas.com> Cc: Biju Das <biju.das@bp.renesas.com> Subject: [cip-dev] [PATCH 4.19.y-cip 39/39] arm64: defconfig: Enable R8A774B1 SoC Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: cip-dev-bounces@lists.cip-project.org Sender: "cip-dev" <cip-dev-bounces@lists.cip-project.org>
Series	Add RZ/G2N SYSC/RST/Clock/PFC support \| expand [4.19.y-cip,00/39] Add RZ/G2N SYSC/RST/Clock/PFC support [4.19.y-cip,01/39] dt-bindings: arm: renesas: Document RZ/G2N SoC DT bindings [4.19.y-cip,02/39] dt-bindings: arm: renesas: Add HopeRun RZ/G2N boards [4.19.y-cip,03/39] soc: renesas: Add Renesas R8A774B1 config option [4.19.y-cip,04/39] soc: renesas: Identify RZ/G2N [4.19.y-cip,05/39] dt-bindings: power: Add r8a774b1 SYSC power domain definitions [4.19.y-cip,06/39] dt-bindings: power: rcar-sysc: Document r8a774b1 sysc [4.19.y-cip,07/39] soc: renesas: rcar-sysc: Prepare for fixing power request conflicts [4.19.y-cip,08/39] soc: renesas: r8a7795-sysc: Fix power request conflicts [4.19.y-cip,09/39] soc: renesas: r8a7796-sysc: Fix power request conflicts [4.19.y-cip,10/39] soc: renesas: r8a77965-sysc: Fix power request conflicts [4.19.y-cip,11/39] soc: renesas: r8a77970-sysc: Fix power request conflicts [4.19.y-cip,12/39] soc: renesas: r8a77980-sysc: Fix power request conflicts [4.19.y-cip,13/39] soc: renesas: r8a77990-sysc: Fix power request conflicts [4.19.y-cip,14/39] soc: renesas: r8a774c0-sysc: Fix power request conflicts [4.19.y-cip,15/39] soc: renesas: rcar-sysc: Add r8a774b1 support [4.19.y-cip,16/39] dt-bindings: reset: rcar-rst: Document r8a774b1 reset module [4.19.y-cip,17/39] soc: renesas: rcar-rst: Add support for RZ/G2N [4.19.y-cip,18/39] dt-bindings: clk: Add r8a774b1 CPG Core Clock Definitions [4.19.y-cip,19/39] dt-bindings: clock: renesas: cpg-mssr: Document r8a774b1 binding [4.19.y-cip,20/39] clk: renesas: cpg-mssr: Add r8a774b1 support [4.19.y-cip,21/39] pinctrl: sh-pfc: r8a77965: Add SATA pins, groups and functions [4.19.y-cip,22/39] pinctrl: sh-pfc: r8a77965: Add Audio clock pin support [4.19.y-cip,23/39] pinctrl: sh-pfc: r8a77965: Add Audio SSI pin support [4.19.y-cip,24/39] pinctrl: sh-pfc: r8a77965: Add VIN[4\|5] groups/functions [4.19.y-cip,25/39] pinctrl: sh-pfc: r8a77965: Add CAN pins, groups and functions [4.19.y-cip,26/39] pinctrl: sh-pfc: r8a77965: Add CAN FD pins, groups and functions [4.19.y-cip,27/39] pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3 [4.19.y-cip,28/39] pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions [4.19.y-cip,29/39] pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions [4.19.y-cip,30/39] pinctrl: sh-pfc: r8a77965: Add I2C{0, 3, 5} pins, groups and functions [4.19.y-cip,31/39] pinctrl: sh-pfc: r8a77965: Add TPU pins, groups and functions [4.19.y-cip,32/39] pinctrl: sh-pfc: r8a77965: Use new macros for non-GPIO pins [4.19.y-cip,33/39] dt-bindings: pinctrl: sh-pfc: Document r8a774b1 PFC support [4.19.y-cip,34/39] pinctrl: sh-pfc: r8a77965: Add R8A774B1 PFC support [4.19.y-cip,35/39] pinctrl: sh-pfc: pfc-r8a77965: Fix typo in pinmux macro for SCL3 [4.19.y-cip,36/39] dt-bindings: serial: sh-sci: Document r8a774b1 bindings [4.19.y-cip,37/39] arm64: dts: renesas: Initial r8a774b1 SoC device tree [4.19.y-cip,38/39] arm64: dts: renesas: Add HiHope RZ/G2N main board support [4.19.y-cip,39/39] arm64: defconfig: Enable R8A774B1 SoC

Commit Message

Biju Das Dec. 18, 2019, 11:33 a.m. UTC

commit d8b178741e5ba571fbcc187c9e3cf9c0eaebf328 upstream.

Enable the Renesas RZ/G2N (R8A774B1) SoC in the ARM64 defconfig.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1568725530-55241-3-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index dbe83fd..0165a2f 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -51,6 +51,7 @@  CONFIG_ARCH_SEATTLE=y
 CONFIG_ARCH_SYNQUACER=y
 CONFIG_ARCH_RENESAS=y
 CONFIG_ARCH_R8A774A1=y
+CONFIG_ARCH_R8A774B1=y
 CONFIG_ARCH_R8A774C0=y
 CONFIG_ARCH_R8A7795=y
 CONFIG_ARCH_R8A7796=y