@@ -26,8 +26,11 @@ static inline void local_flush_tlb_all(void)
static inline void flush_tlb_all(void)
{
- //TODO
- local_flush_tlb_all();
+ dsb(ishst);
+ /* TLBIALLIS */
+ asm volatile("mcr p15, 0, %0, c8, c3, 0" :: "r" (0));
+ dsb(ish);
+ isb();
}
static inline void flush_tlb_page(unsigned long vaddr)
@@ -41,6 +44,7 @@ static inline void flush_tlb_page(unsigned long vaddr)
static inline void flush_dcache_addr(unsigned long vaddr)
{
+ /* DCCIMVAC */
asm volatile("mcr p15, 0, %0, c7, c14, 1" :: "r" (vaddr));
}
flush_tlb_all performs a TLBIALL, which invalidates the entire TLB and affects only the executing PE; translation table walks are now Inner Shareable, so execute a TLBIALLIS (invalidate TLB Inner Shareable) instead. TLBIALLIS is the equivalent of TLBIALL [1] when the multiprocessing extensions are implemented, which are mandated by the virtualization extensions. Also add the necessary barriers to tlb_flush_all and a comment to flush_dcache_addr stating what instruction is uses (unsurprisingly, it's DCCIMVAC, which does a dcache clean and invalidate by VA to PoC). [1] ARM DDI 0406C.d, section B3.10.6 Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> --- lib/arm/asm/mmu.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)