| Message ID | 20200107044827.471355-7-david@gibson.dropbear.id.au (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/ppc: Correct some errors with real mode handling | expand |
On 1/7/20 5:48 AM, David Gibson wrote: > Currently we create the Real Mode Offset Register (RMOR) on all Book3S cpus > from POWER7 onwards. However the translation mode which the RMOR controls > is no longer supported in POWER9, and so the register has been removed from > the architecture. > > Remove it from our model on POWER9 and POWER10. > > Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> > --- > target/ppc/translate_init.inc.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c > index 436d0d5a51..893fb12e90 100644 > --- a/target/ppc/translate_init.inc.c > +++ b/target/ppc/translate_init.inc.c > @@ -8003,12 +8003,16 @@ static void gen_spr_book3s_ids(CPUPPCState *env) > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > 0x00000000); > - spr_register_hv(env, SPR_RMOR, "RMOR", > + spr_register_hv(env, SPR_HRMOR, "HRMOR", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > 0x00000000); > - spr_register_hv(env, SPR_HRMOR, "HRMOR", > +} > + > +static void gen_spr_rmor(CPUPPCState *env) > +{ > + spr_register_hv(env, SPR_RMOR, "RMOR", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > @@ -8522,6 +8526,7 @@ static void init_proc_POWER7(CPUPPCState *env) > > /* POWER7 Specific Registers */ > gen_spr_book3s_ids(env); > + gen_spr_rmor(env); > gen_spr_amr(env); > gen_spr_book3s_purr(env); > gen_spr_power5p_common(env); > @@ -8663,6 +8668,7 @@ static void init_proc_POWER8(CPUPPCState *env) > > /* POWER8 Specific Registers */ > gen_spr_book3s_ids(env); > + gen_spr_rmor(env); > gen_spr_amr(env); > gen_spr_iamr(env); > gen_spr_book3s_purr(env); >
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 436d0d5a51..893fb12e90 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8003,12 +8003,16 @@ static void gen_spr_book3s_ids(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - spr_register_hv(env, SPR_RMOR, "RMOR", + spr_register_hv(env, SPR_HRMOR, "HRMOR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - spr_register_hv(env, SPR_HRMOR, "HRMOR", +} + +static void gen_spr_rmor(CPUPPCState *env) +{ + spr_register_hv(env, SPR_RMOR, "RMOR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -8522,6 +8526,7 @@ static void init_proc_POWER7(CPUPPCState *env) /* POWER7 Specific Registers */ gen_spr_book3s_ids(env); + gen_spr_rmor(env); gen_spr_amr(env); gen_spr_book3s_purr(env); gen_spr_power5p_common(env); @@ -8663,6 +8668,7 @@ static void init_proc_POWER8(CPUPPCState *env) /* POWER8 Specific Registers */ gen_spr_book3s_ids(env); + gen_spr_rmor(env); gen_spr_amr(env); gen_spr_iamr(env); gen_spr_book3s_purr(env);
Currently we create the Real Mode Offset Register (RMOR) on all Book3S cpus from POWER7 onwards. However the translation mode which the RMOR controls is no longer supported in POWER9, and so the register has been removed from the architecture. Remove it from our model on POWER9 and POWER10. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> --- target/ppc/translate_init.inc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)