[CI] drm/i915/gt: Always reset the timeslice after a context switch
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Message ID 20200113214546.1990139-1-chris@chris-wilson.co.uk
State New
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  • [CI] drm/i915/gt: Always reset the timeslice after a context switch
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Commit Message

Chris Wilson Jan. 13, 2020, 9:45 p.m. UTC
Currently, we reset the timer after a pre-eemption event. This has the
side-effect that the timeslice runs into the second context after the
first is completed after a normal promotion event, causing the second
context to be swapped out early and switched for a third context. To be
more fair, we want to reset the clock after promotion as well.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200113104442.1753973-1-chris@chris-wilson.co.uk
 drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff mbox series

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 9af1b2b493f4..9e430590fb3a 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1694,7 +1694,7 @@  active_timeslice(const struct intel_engine_cs *engine)
 	const struct i915_request *rq = *engine->execlists.active;
-	if (i915_request_completed(rq))
+	if (!rq || i915_request_completed(rq))
 		return 0;
 	if (engine->execlists.switch_priority_hint < effective_prio(rq))
@@ -2285,7 +2285,6 @@  static void process_csb(struct intel_engine_cs *engine)
 			/* Point active to the new ELSP; prevent overwriting */
 			WRITE_ONCE(execlists->active, execlists->pending);
-			set_timeslice(engine);
 			if (!inject_preempt_hang(execlists))
 				ring_set_paused(engine, 0);
@@ -2326,6 +2325,7 @@  static void process_csb(struct intel_engine_cs *engine)
 	} while (head != tail);
 	execlists->csb_head = head;
+	set_timeslice(engine);
 	 * Gen11 has proven to fail wrt global observation point between