diff mbox series

drm/i915/tgl: Program MBUS_ABOX{1, 2}_CTL during display init

Message ID 20200116014855.3615366-1-matthew.d.roper@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/tgl: Program MBUS_ABOX{1, 2}_CTL during display init | expand

Commit Message

Matt Roper Jan. 16, 2020, 1:48 a.m. UTC 
On gen11 we only needed to program MBus credits into MBUS_ABOX_CTL
during display initialization, but on gen12 we're now supposed to
program the same values into MBUS_ABOX1_CTL and MBUS_ABOX2_CTL as well.

Bspec: 49213
Bspec: 50096
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++++
 drivers/gpu/drm/i915/i915_reg.h                    | 2 ++
 2 files changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 21561acfa3ac..761be9fcaf10 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4474,6 +4474,10 @@  static void icl_mbus_init(struct drm_i915_private *dev_priv)
 	      MBUS_ABOX_BW_CREDIT(1);
 
 	I915_WRITE(MBUS_ABOX_CTL, val);
+	if (INTEL_GEN(dev_priv) >= 12) {
+		I915_WRITE(MBUS_ABOX1_CTL, val);
+		I915_WRITE(MBUS_ABOX2_CTL, val);
+	}
 }
 
 static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e5949edf2a8..ef191a0278ac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2860,6 +2860,8 @@  static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MI_ARB_STATE	_MMIO(0x20e4) /* 915+ only */
 
 #define MBUS_ABOX_CTL			_MMIO(0x45038)
+#define MBUS_ABOX1_CTL			_MMIO(0x45048)
+#define MBUS_ABOX2_CTL			_MMIO(0x4504C)
 #define MBUS_ABOX_BW_CREDIT_MASK	(3 << 20)
 #define MBUS_ABOX_BW_CREDIT(x)		((x) << 20)
 #define MBUS_ABOX_B_CREDIT_MASK		(0xF << 16)