diff mbox series

clk: imx: pll14xx: Add new frequency entries for pll1443x table

Message ID 1579157449-7602-1-git-send-email-Anson.Huang@nxp.com (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series clk: imx: pll14xx: Add new frequency entries for pll1443x table | expand

Commit Message

Anson Huang Jan. 16, 2020, 6:50 a.m. UTC
Add new frequency entries to pll1443x table to meet different
display settings requirement.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
 drivers/clk/imx/clk-pll14xx.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Peng Fan Jan. 16, 2020, 7:26 a.m. UTC | #1
> Subject: [PATCH] clk: imx: pll14xx: Add new frequency entries for pll1443x
> table
> 
> Add new frequency entries to pll1443x table to meet different display settings
> requirement.

Reviewed-by: Peng Fan <peng.fan@nxp.com>

Regards,
Peng.

> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
>  drivers/clk/imx/clk-pll14xx.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index
> 5b0519a..37e311e 100644
> --- a/drivers/clk/imx/clk-pll14xx.c
> +++ b/drivers/clk/imx/clk-pll14xx.c
> @@ -55,8 +55,10 @@ static const struct imx_pll14xx_rate_table
> imx_pll1416x_tbl[] = {  };
> 
>  static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
> +	PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
>  	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
>  	PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
> +	PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
>  	PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
>  	PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),  };
> --
> 2.7.4
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index 5b0519a..37e311e 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -55,8 +55,10 @@  static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
 };
 
 static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
+	PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
 	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
 	PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
+	PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
 	PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
 	PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
 };