[1/2] ARM: dts: at91: at91sam9n12: properly order shdwc node
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Message ID 20200116173453.427267-1-alexandre.belloni@bootlin.com
State New
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  • [1/2] ARM: dts: at91: at91sam9n12: properly order shdwc node
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Commit Message

Alexandre Belloni Jan. 16, 2020, 5:34 p.m. UTC
The shdwc node is not at is correct place, order it properly

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
 arch/arm/boot/dts/at91sam9n12.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Patch
diff mbox series

diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index ea675174432e..d6eacb2e3792 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -396,6 +396,12 @@  rstc@fffffe00 {
 				clocks = <&clk32k>;
 			};
 
+			shdwc@fffffe10 {
+				compatible = "atmel,at91sam9x5-shdwc";
+				reg = <0xfffffe10 0x10>;
+				clocks = <&clk32k>;
+			};
+
 			pit: timer@fffffe30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffe30 0xf>;
@@ -403,12 +409,6 @@  pit: timer@fffffe30 {
 				clocks = <&mck>;
 			};
 
-			shdwc@fffffe10 {
-				compatible = "atmel,at91sam9x5-shdwc";
-				reg = <0xfffffe10 0x10>;
-				clocks = <&clk32k>;
-			};
-
 			sckc@fffffe50 {
 				compatible = "atmel,at91sam9x5-sckc";
 				reg = <0xfffffe50 0x4>;