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Mon, 20 Jan 2020 05:10:15 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.85.251) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Mon, 20 Jan 2020 05:10:14 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH 1/8] ARM: at91: pm: use proper master clock register offset Date: Mon, 20 Jan 2020 14:10:01 +0200 Message-ID: <1579522208-19523-2-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1579522208-19523-1-git-send-email-claudiu.beznea@microchip.com> References: <1579522208-19523-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200120_041018_554297_5248533D X-CRM114-Status: GOOD ( 11.14 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [68.232.153.233 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Beznea , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org SAM9X60's PMC has different master clock register offset than the other SoCs' PMC. Due to this, specify master clock register offset based on PMC compatible and pass it to pm_suspend.S since it is also needed in there. When PM part for SAM9X60 was published the SAM9X60's PMC (commit f6deae46039c ("clk: at91: add sam9x60 pmc driver")) wasn't integrated. Fixes: fd2280a1829b ("ARM: at91: pm: initial PM support for SAM9X60") Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/pm.c | 28 +++++++++++++++++++++++----- arch/arm/mach-at91/pm.h | 1 + arch/arm/mach-at91/pm_data-offsets.c | 2 ++ arch/arm/mach-at91/pm_suspend.S | 32 ++++++++++++++++++++------------ 4 files changed, 46 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 374b9d155558..ae7b148febd9 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -736,13 +736,30 @@ static void __init at91_pm_modes_init(void) struct pmc_info { unsigned long uhp_udp_mask; + unsigned long mckr; }; static const struct pmc_info pmc_infos[] __initconst = { - { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP }, - { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP }, - { .uhp_udp_mask = AT91SAM926x_PMC_UHP }, - { .uhp_udp_mask = 0 }, + { + .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP, + .mckr = 0x30, + }, + + { + .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, + .mckr = 0x30, + }, + { + .uhp_udp_mask = AT91SAM926x_PMC_UHP, + .mckr = 0x30, + }, + { .uhp_udp_mask = 0, + .mckr = 0x30, + }, + { + .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, + .mckr = 0x28, + }, }; static const struct of_device_id atmel_pmc_ids[] __initconst = { @@ -757,7 +774,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = { { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] }, { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, - { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[1] }, + { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, { /* sentinel */ }, }; @@ -779,6 +796,7 @@ static void __init at91_pm_init(void (*pm_idle)(void)) pmc = of_id->data; soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask; + soc_pm.data.pmc_mckr_offset = pmc->mckr; if (pm_idle) arm_pm_idle = pm_idle; diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 9fa4f483f2b5..6f7f4236865a 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -33,6 +33,7 @@ struct at91_pm_data { void __iomem *sfrbu; unsigned int standby_mode; unsigned int suspend_mode; + unsigned int pmc_mckr_offset; }; #endif diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_data-offsets.c index f2d893c03cd9..dfcbe626865c 100644 --- a/arch/arm/mach-at91/pm_data-offsets.c +++ b/arch/arm/mach-at91/pm_data-offsets.c @@ -12,6 +12,8 @@ int main(void) DEFINE(PM_DATA_MODE, offsetof(struct at91_pm_data, mode)); DEFINE(PM_DATA_SHDWC, offsetof(struct at91_pm_data, shdwc)); DEFINE(PM_DATA_SFRBU, offsetof(struct at91_pm_data, sfrbu)); + DEFINE(PM_DATA_PMC_MCKR_OFFSET, offsetof(struct at91_pm_data, + pmc_mckr_offset)); return 0; } diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index ed57c879d4e1..52b262d56cfd 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -93,6 +93,8 @@ ENTRY(at91_pm_suspend_in_sram) str tmp1, .memtype ldr tmp1, [r0, #PM_DATA_MODE] str tmp1, .pm_mode + ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] + str tmp1, .mckr_offset /* Both ldrne below are here to preload their address in the TLB */ ldr tmp1, [r0, #PM_DATA_SHDWC] str tmp1, .shdwc @@ -138,9 +140,10 @@ ENDPROC(at91_pm_suspend_in_sram) ENTRY(at91_backup_mode) /* Switch the master clock source to slow clock. */ ldr pmc, .pmc_base - ldr tmp1, [pmc, #AT91_PMC_MCKR] + ldr tmp2, .mckr_offset + ldr tmp1, [pmc, tmp2] bic tmp1, tmp1, #AT91_PMC_CSS - str tmp1, [pmc, #AT91_PMC_MCKR] + str tmp1, [pmc, tmp2] wait_mckrdy @@ -218,6 +221,7 @@ ENDPROC(at91_backup_mode) */ .macro at91_pm_ulp1_mode ldr pmc, .pmc_base + ldr tmp2, .mckr_offset /* Save RC oscillator state and check if it is enabled. */ ldr tmp1, [pmc, #AT91_PMC_SR] @@ -254,10 +258,10 @@ ENDPROC(at91_backup_mode) str tmp1, [pmc, #AT91_CKGR_MOR] /* Switch the master clock source to main clock */ - ldr tmp1, [pmc, #AT91_PMC_MCKR] + ldr tmp1, [pmc, tmp2] bic tmp1, tmp1, #AT91_PMC_CSS orr tmp1, tmp1, #AT91_PMC_CSS_MAIN - str tmp1, [pmc, #AT91_PMC_MCKR] + str tmp1, [pmc, tmp2] wait_mckrdy @@ -280,9 +284,9 @@ ENDPROC(at91_backup_mode) wait_moscrdy /* Switch the master clock source to slow clock */ - ldr tmp1, [pmc, #AT91_PMC_MCKR] + ldr tmp1, [pmc, tmp2] bic tmp1, tmp1, #AT91_PMC_CSS - str tmp1, [pmc, #AT91_PMC_MCKR] + str tmp1, [pmc, tmp2] wait_mckrdy @@ -296,10 +300,10 @@ ENDPROC(at91_backup_mode) wait_moscsels /* Switch the master clock source to main clock */ - ldr tmp1, [pmc, #AT91_PMC_MCKR] + ldr tmp1, [pmc, tmp2] bic tmp1, tmp1, #AT91_PMC_CSS orr tmp1, tmp1, #AT91_PMC_CSS_MAIN - str tmp1, [pmc, #AT91_PMC_MCKR] + str tmp1, [pmc, tmp2] wait_mckrdy @@ -325,16 +329,17 @@ ENDPROC(at91_backup_mode) ENTRY(at91_ulp_mode) ldr pmc, .pmc_base + ldr tmp2, .mckr_offset /* Save Master clock setting */ - ldr tmp1, [pmc, #AT91_PMC_MCKR] + ldr tmp1, [pmc, tmp2] str tmp1, .saved_mckr /* * Set the Master clock source to slow clock */ bic tmp1, tmp1, #AT91_PMC_CSS - str tmp1, [pmc, #AT91_PMC_MCKR] + str tmp1, [pmc, tmp2] wait_mckrdy @@ -355,8 +360,9 @@ ulp_exit: /* * Restore master clock setting */ - ldr tmp1, .saved_mckr - str tmp1, [pmc, #AT91_PMC_MCKR] + ldr tmp1, .mckr_offset + ldr tmp2, .saved_mckr + str tmp2, [pmc, tmp1] wait_mckrdy @@ -502,6 +508,8 @@ ENDPROC(at91_sramc_self_refresh) .word 0 .pm_mode: .word 0 +.mckr_offset: + .word 0 .saved_mckr: .word 0 .saved_sam9_lpr: