@@ -11,6 +11,7 @@
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_lrc_reg.h"
+#include "gt/intel_mocs.h"
#include "gt/intel_ring.h"
#include "intel_guc_submission.h"
@@ -501,6 +502,32 @@ static void guc_reset_finish(struct intel_engine_cs *engine)
atomic_read(&execlists->tasklet.count));
}
+static void hwsp_setup(struct intel_engine_cs *engine)
+{
+ intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
+
+ ENGINE_WRITE(engine, RING_HWS_PGA,
+ i915_ggtt_offset(engine->status_page.vma));
+ ENGINE_POSTING_READ(engine, RING_HWS_PGA);
+}
+
+static int guc_submission_resume(struct intel_engine_cs *engine)
+{
+ intel_engine_apply_workarounds(engine);
+ intel_engine_apply_whitelist(engine);
+
+ intel_mocs_init_engine(engine);
+
+ intel_engine_reset_breadcrumbs(engine);
+
+ hwsp_setup(engine);
+
+ /* pre-gen11 requires explicit enabling of the execlists */
+ GEM_BUG_ON(INTEL_GEN(engine->i915) < 11);
+
+ return 0;
+}
+
static int guc_submission_request_alloc(struct i915_request *request)
{
int ret;
@@ -745,6 +772,8 @@ static void guc_submission_default_vfuncs(struct intel_engine_cs *engine)
{
/* Default vfuncs which can be overriden by each engine. */
+ engine->resume = guc_submission_resume;
+
engine->request_alloc = guc_submission_request_alloc;
engine->emit_init_breadcrumb = emit_init_breadcrumb;
Similar to the execlists one, but we don't handle the STOP_RING (because GuC owns the engine status) and we leave the CSB fifo at 6 deep. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Matthew Brost <matthew.brost@intel.com> --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+)