Message ID | 20200128235241.169694-2-jose.souza@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [1/2] drm/i915/display/fbc: Make fences a nice-to-have for GEN9+ | expand |
On Tue, Jan 28, 2020 at 03:52:41PM -0800, José Roberto de Souza wrote: > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > dgfx platforms do not support CPU fence and FBC host tracking so > lets avoid write to removed registers. > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > index 1f0d24a1dec1..12900b8ce28e 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -314,7 +314,12 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) > break; > } > > - if (params->fence_id >= 0) { > + if (IS_DGFX(dev_priv)) { > + /* > + * dGFX GPUs don't have apperture or fences and only rely on FBC > + * render nuke to track frontbuffer modifications > + */ > + } else if (params->fence_id >= 0) { > dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; > intel_de_write(dev_priv, SNB_DPFC_CTL_SA, > SNB_CPU_FENCE_ENABLE | params->fence_id); if (fence) { do stuff } else if (num_fences) { do other stuff } > -- > 2.25.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, 2020-01-29 at 13:42 +0200, Ville Syrjälä wrote: > On Tue, Jan 28, 2020 at 03:52:41PM -0800, José Roberto de Souza > wrote: > > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > > > dgfx platforms do not support CPU fence and FBC host tracking so > > lets avoid write to removed registers. > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Cc: Matt Roper <matthew.d.roper@intel.com> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com > > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++++++- > > 1 file changed, 6 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > > b/drivers/gpu/drm/i915/display/intel_fbc.c > > index 1f0d24a1dec1..12900b8ce28e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > @@ -314,7 +314,12 @@ static void gen7_fbc_activate(struct > > drm_i915_private *dev_priv) > > break; > > } > > > > - if (params->fence_id >= 0) { > > + if (IS_DGFX(dev_priv)) { > > + /* > > + * dGFX GPUs don't have apperture or fences and only > > rely on FBC > > + * render nuke to track frontbuffer modifications > > + */ > > + } else if (params->fence_id >= 0) { > > dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; > > intel_de_write(dev_priv, SNB_DPFC_CTL_SA, > > SNB_CPU_FENCE_ENABLE | params- > > >fence_id); > > if (fence) { > do stuff > } else if (num_fences) { > do other stuff > } Did not get what you want here. It is covering all cases: - DGFX that don't have the registers - Setting the registers when fence_id >= 0 - Clearing the register when fences_id == -1 > > > -- > > 2.25.0 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, Feb 04, 2020 at 02:06:23AM +0000, Souza, Jose wrote: > On Wed, 2020-01-29 at 13:42 +0200, Ville Syrjälä wrote: > > On Tue, Jan 28, 2020 at 03:52:41PM -0800, José Roberto de Souza > > wrote: > > > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > > > > > dgfx platforms do not support CPU fence and FBC host tracking so > > > lets avoid write to removed registers. > > > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > Cc: Matt Roper <matthew.d.roper@intel.com> > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com > > > > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++++++- > > > 1 file changed, 6 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > > > b/drivers/gpu/drm/i915/display/intel_fbc.c > > > index 1f0d24a1dec1..12900b8ce28e 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > > @@ -314,7 +314,12 @@ static void gen7_fbc_activate(struct > > > drm_i915_private *dev_priv) > > > break; > > > } > > > > > > - if (params->fence_id >= 0) { > > > + if (IS_DGFX(dev_priv)) { > > > + /* > > > + * dGFX GPUs don't have apperture or fences and only > > > rely on FBC > > > + * render nuke to track frontbuffer modifications > > > + */ > > > + } else if (params->fence_id >= 0) { > > > dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; > > > intel_de_write(dev_priv, SNB_DPFC_CTL_SA, > > > SNB_CPU_FENCE_ENABLE | params- > > > >fence_id); > > > > if (fence) { > > do stuff > > } else if (num_fences) { > > do other stuff > > } > > Did not get what you want here. Don't add a silly looking empty if block. And don't make the assumption that dgfx is the only thing that has no fences, instead actually check if we have fences or not. > It is covering all cases: > - DGFX that don't have the registers > - Setting the registers when fence_id >= 0 > - Clearing the register when fences_id == -1 > > > > > > -- > > > 2.25.0 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 1f0d24a1dec1..12900b8ce28e 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -314,7 +314,12 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) break; } - if (params->fence_id >= 0) { + if (IS_DGFX(dev_priv)) { + /* + * dGFX GPUs don't have apperture or fences and only rely on FBC + * render nuke to track frontbuffer modifications + */ + } else if (params->fence_id >= 0) { dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; intel_de_write(dev_priv, SNB_DPFC_CTL_SA, SNB_CPU_FENCE_ENABLE | params->fence_id);