| Message ID | 20200130112510.15154-5-eric.auger@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: arm64: PMUv3 Event Counter Tests | expand |
On Thu, 30 Jan 2020 at 11:25, Eric Auger <eric.auger@redhat.com> wrote: > > If event counters are implemented check the common events > required by the PMUv3 are implemented. > > Some are unconditionally required (SW_INCR, CPU_CYCLES, > either INST_RETIRED or INST_SPEC). Some others only are > required if the implementation implements some other features. > > Check those wich are unconditionally required. > > This test currently fails on TCG as neither INST_RETIRED > or INST_SPEC are supported. > > Signed-off-by: Eric Auger <eric.auger@redhat.com> > > --- > > +static bool is_event_supported(uint32_t n, bool warn) > +{ > + uint64_t pmceid0 = read_sysreg(pmceid0_el0); > + uint64_t pmceid1 = read_sysreg_s(PMCEID1_EL0); > + bool supported; > + uint64_t reg; > + > + /* > + * The low 32-bits of PMCEID0/1 respectly describe "respectively" > + * event support for events 0-31/32-63. Their High > + * 32-bits describe support for extended events > + * starting at 0x4000, using the same split. > + */ > + if (n >= 0x0 && n <= 0x3F) > + reg = (pmceid0 & 0xFFFFFFFF) | ((pmceid1 & 0xFFFFFFFF) << 32); > + else if (n >= 0x4000 && n <= 0x403F) > + reg = (pmceid0 >> 32) | ((pmceid1 >> 32) << 32); > + else > + abort(); > + > + supported = reg & (1UL << (n & 0x3F)); > + > + if (!supported && warn) > + report_info("event %d is not supported", n); > + return supported; > +} > + > +static void test_event_introspection(void) > +{ > + bool required_events; > + > + if (!pmu.nb_implemented_counters) { > + report_skip("No event counter, skip ..."); > + return; > + } > + > + /* PMUv3 requires an implementation includes some common events */ > + required_events = is_event_supported(0x0, true) /* SW_INCR */ && > + is_event_supported(0x11, true) /* CPU_CYCLES */ && > + (is_event_supported(0x8, true) /* INST_RETIRED */ || > + is_event_supported(0x1B, true) /* INST_PREC */); > + > + if (pmu.version == 0x4) { This condition will only test for v8.1-required events if the PMU is exactly 8.1, so you lose coverage if the implementation happens to support ARMv8.4-PMU. Hopefully you have already bailed out for "ID_AA64DFR0_EL1.PMUVer == 0xf" which means "non-standard IMPDEF PMU", in which case you can just check >= 0x4. > + /* ARMv8.1 PMU: STALL_FRONTEND and STALL_BACKEND are required */ > + required_events = required_events && > + is_event_supported(0x23, true) && > + is_event_supported(0x24, true); > + } > + > + report(required_events, "Check required events are implemented"); > +} > + > #endif thanks -- PMM
On Thu, 30 Jan 2020 at 11:25, Eric Auger <eric.auger@redhat.com> wrote: > > If event counters are implemented check the common events > required by the PMUv3 are implemented. > > Some are unconditionally required (SW_INCR, CPU_CYCLES, > either INST_RETIRED or INST_SPEC). Some others only are > required if the implementation implements some other features. > > Check those wich are unconditionally required. > > This test currently fails on TCG as neither INST_RETIRED > or INST_SPEC are supported. > > Signed-off-by: Eric Auger <eric.auger@redhat.com> > > +static bool is_event_supported(uint32_t n, bool warn) > +{ > + uint64_t pmceid0 = read_sysreg(pmceid0_el0); > + uint64_t pmceid1 = read_sysreg_s(PMCEID1_EL0); > + bool supported; > + uint64_t reg; > + > + /* > + * The low 32-bits of PMCEID0/1 respectly describe > + * event support for events 0-31/32-63. Their High > + * 32-bits describe support for extended events > + * starting at 0x4000, using the same split. > + */ > + if (n >= 0x0 && n <= 0x3F) > + reg = (pmceid0 & 0xFFFFFFFF) | ((pmceid1 & 0xFFFFFFFF) << 32); > + else if (n >= 0x4000 && n <= 0x403F) > + reg = (pmceid0 >> 32) | ((pmceid1 >> 32) << 32); > + else > + abort(); > + > + supported = reg & (1UL << (n & 0x3F)); > + > + if (!supported && warn) > + report_info("event %d is not supported", n); As with satisfy_prerequisites(), printing this with "0x%x" would probably be more helpful to most users. thanks -- PMM
Hi Peter, On 2/11/20 4:33 PM, Peter Maydell wrote: > On Thu, 30 Jan 2020 at 11:25, Eric Auger <eric.auger@redhat.com> wrote: >> >> If event counters are implemented check the common events >> required by the PMUv3 are implemented. >> >> Some are unconditionally required (SW_INCR, CPU_CYCLES, >> either INST_RETIRED or INST_SPEC). Some others only are >> required if the implementation implements some other features. >> >> Check those wich are unconditionally required. >> >> This test currently fails on TCG as neither INST_RETIRED >> or INST_SPEC are supported. >> >> Signed-off-by: Eric Auger <eric.auger@redhat.com> >> >> --- >> > >> +static bool is_event_supported(uint32_t n, bool warn) >> +{ >> + uint64_t pmceid0 = read_sysreg(pmceid0_el0); >> + uint64_t pmceid1 = read_sysreg_s(PMCEID1_EL0); >> + bool supported; >> + uint64_t reg; >> + >> + /* >> + * The low 32-bits of PMCEID0/1 respectly describe > > "respectively" > >> + * event support for events 0-31/32-63. Their High >> + * 32-bits describe support for extended events >> + * starting at 0x4000, using the same split. >> + */ >> + if (n >= 0x0 && n <= 0x3F) >> + reg = (pmceid0 & 0xFFFFFFFF) | ((pmceid1 & 0xFFFFFFFF) << 32); >> + else if (n >= 0x4000 && n <= 0x403F) >> + reg = (pmceid0 >> 32) | ((pmceid1 >> 32) << 32); >> + else >> + abort(); >> + >> + supported = reg & (1UL << (n & 0x3F)); >> + >> + if (!supported && warn) >> + report_info("event %d is not supported", n); >> + return supported; >> +} >> + >> +static void test_event_introspection(void) >> +{ >> + bool required_events; >> + >> + if (!pmu.nb_implemented_counters) { >> + report_skip("No event counter, skip ..."); >> + return; >> + } >> + >> + /* PMUv3 requires an implementation includes some common events */ >> + required_events = is_event_supported(0x0, true) /* SW_INCR */ && >> + is_event_supported(0x11, true) /* CPU_CYCLES */ && >> + (is_event_supported(0x8, true) /* INST_RETIRED */ || >> + is_event_supported(0x1B, true) /* INST_PREC */); >> + >> + if (pmu.version == 0x4) { > > This condition will only test for v8.1-required events if the PMU > is exactly 8.1, so you lose coverage if the implementation happens > to support ARMv8.4-PMU. Hopefully you have already bailed out > for "ID_AA64DFR0_EL1.PMUVer == 0xf" which means "non-standard IMPDEF > PMU", in which case you can just check >= 0x4. OK thanks Eric > >> + /* ARMv8.1 PMU: STALL_FRONTEND and STALL_BACKEND are required */ >> + required_events = required_events && >> + is_event_supported(0x23, true) && >> + is_event_supported(0x24, true); >> + } >> + >> + report(required_events, "Check required events are implemented"); >> +} >> + >> #endif > > thanks > -- PMM >
Hi Peter, On 2/11/20 5:28 PM, Peter Maydell wrote: > On Thu, 30 Jan 2020 at 11:25, Eric Auger <eric.auger@redhat.com> wrote: >> >> If event counters are implemented check the common events >> required by the PMUv3 are implemented. >> >> Some are unconditionally required (SW_INCR, CPU_CYCLES, >> either INST_RETIRED or INST_SPEC). Some others only are >> required if the implementation implements some other features. >> >> Check those wich are unconditionally required. >> >> This test currently fails on TCG as neither INST_RETIRED >> or INST_SPEC are supported. >> >> Signed-off-by: Eric Auger <eric.auger@redhat.com> >> > >> +static bool is_event_supported(uint32_t n, bool warn) >> +{ >> + uint64_t pmceid0 = read_sysreg(pmceid0_el0); >> + uint64_t pmceid1 = read_sysreg_s(PMCEID1_EL0); >> + bool supported; >> + uint64_t reg; >> + >> + /* >> + * The low 32-bits of PMCEID0/1 respectly describe >> + * event support for events 0-31/32-63. Their High >> + * 32-bits describe support for extended events >> + * starting at 0x4000, using the same split. >> + */ >> + if (n >= 0x0 && n <= 0x3F) >> + reg = (pmceid0 & 0xFFFFFFFF) | ((pmceid1 & 0xFFFFFFFF) << 32); >> + else if (n >= 0x4000 && n <= 0x403F) >> + reg = (pmceid0 >> 32) | ((pmceid1 >> 32) << 32); >> + else >> + abort(); >> + >> + supported = reg & (1UL << (n & 0x3F)); >> + >> + if (!supported && warn) >> + report_info("event %d is not supported", n); > > As with satisfy_prerequisites(), printing this with "0x%x" > would probably be more helpful to most users. OK Thanks Eric > > thanks > -- PMM >
On Thu, 30 Jan 2020 12:25:05 +0100 Eric Auger <eric.auger@redhat.com> wrote: Hi, > If event counters are implemented check the common events > required by the PMUv3 are implemented. > > Some are unconditionally required (SW_INCR, CPU_CYCLES, > either INST_RETIRED or INST_SPEC). Some others only are > required if the implementation implements some other features. > > Check those wich are unconditionally required. > > This test currently fails on TCG as neither INST_RETIRED > or INST_SPEC are supported. > > Signed-off-by: Eric Auger <eric.auger@redhat.com> > > --- > > v1 -> v2: > - fix is_event_supported() > - fix boolean condition for PMU v4 > - fix PMCEID0 definition > > RFC ->v1: > - add a comment to explain the PMCEID0/1 splits > --- > arm/pmu.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++ > arm/unittests.cfg | 6 +++++ > 2 files changed, 68 insertions(+) > > diff --git a/arm/pmu.c b/arm/pmu.c > index d24857e..4a26a76 100644 > --- a/arm/pmu.c > +++ b/arm/pmu.c > @@ -101,6 +101,10 @@ static inline void precise_instrs_loop(int loop, uint32_t pmcr) > : [pmcr] "r" (pmcr), [z] "r" (0) > : "cc"); > } > + > +/* event counter tests only implemented for aarch64 */ > +static void test_event_introspection(void) {} > + > #elif defined(__aarch64__) > #define ID_AA64DFR0_PERFMON_SHIFT 8 > #define ID_AA64DFR0_PERFMON_MASK 0xf > @@ -139,6 +143,61 @@ static inline void precise_instrs_loop(int loop, uint32_t pmcr) > : [pmcr] "r" (pmcr) > : "cc"); > } > + > +#define PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) > + > +static bool is_event_supported(uint32_t n, bool warn) > +{ > + uint64_t pmceid0 = read_sysreg(pmceid0_el0); > + uint64_t pmceid1 = read_sysreg_s(PMCEID1_EL0); > + bool supported; > + uint64_t reg; > + > + /* > + * The low 32-bits of PMCEID0/1 respectly describe > + * event support for events 0-31/32-63. Their High > + * 32-bits describe support for extended events > + * starting at 0x4000, using the same split. > + */ > + if (n >= 0x0 && n <= 0x3F) > + reg = (pmceid0 & 0xFFFFFFFF) | ((pmceid1 & 0xFFFFFFFF) << 32); > + else if (n >= 0x4000 && n <= 0x403F) > + reg = (pmceid0 >> 32) | ((pmceid1 >> 32) << 32); > + else > + abort(); > + > + supported = reg & (1UL << (n & 0x3F)); > + > + if (!supported && warn) > + report_info("event %d is not supported", n); > + return supported; > +} > + > +static void test_event_introspection(void) > +{ > + bool required_events; > + > + if (!pmu.nb_implemented_counters) { > + report_skip("No event counter, skip ..."); > + return; > + } > + > + /* PMUv3 requires an implementation includes some common events */ > + required_events = is_event_supported(0x0, true) /* SW_INCR */ && > + is_event_supported(0x11, true) /* CPU_CYCLES */ && > + (is_event_supported(0x8, true) /* INST_RETIRED */ || > + is_event_supported(0x1B, true) /* INST_PREC */); > + > + if (pmu.version == 0x4) { I think this should read >= 0x4, since those requirements are stacked on top of the prevision revision's requirements. Even better with some symbolic name. With that fixed: Reviewed-by: Andre Przywara <andre.przywara@arm.com> Cheers, Andre > + /* ARMv8.1 PMU: STALL_FRONTEND and STALL_BACKEND are required */ > + required_events = required_events && > + is_event_supported(0x23, true) && > + is_event_supported(0x24, true); > + } > + > + report(required_events, "Check required events are implemented"); > +} > + > #endif > > /* > @@ -326,6 +385,9 @@ int main(int argc, char *argv[]) > "Monotonically increasing cycle count"); > report(check_cpi(cpi), "Cycle/instruction ratio"); > pmccntr64_test(); > + } else if (strcmp(argv[1], "event-introspection") == 0) { > + report_prefix_push(argv[1]); > + test_event_introspection(); > } else { > report_abort("Unknown sub-test '%s'", argv[1]); > } > diff --git a/arm/unittests.cfg b/arm/unittests.cfg > index 79f0d7a..4433ef3 100644 > --- a/arm/unittests.cfg > +++ b/arm/unittests.cfg > @@ -66,6 +66,12 @@ file = pmu.flat > groups = pmu > extra_params = -append 'cycle-counter 0' > > +[pmu-event-introspection] > +file = pmu.flat > +groups = pmu > +arch = arm64 > +extra_params = -append 'event-introspection' > + > # Test PMU support (TCG) with -icount IPC=1 > #[pmu-tcg-icount-1] > #file = pmu.flat
On Thu, Jan 30, 2020 at 12:25:05PM +0100, Eric Auger wrote: > If event counters are implemented check the common events > required by the PMUv3 are implemented. > > Some are unconditionally required (SW_INCR, CPU_CYCLES, > either INST_RETIRED or INST_SPEC). Some others only are > required if the implementation implements some other features. > > Check those wich are unconditionally required. > > This test currently fails on TCG as neither INST_RETIRED > or INST_SPEC are supported. > > Signed-off-by: Eric Auger <eric.auger@redhat.com> > > --- > > v1 -> v2: > - fix is_event_supported() > - fix boolean condition for PMU v4 > - fix PMCEID0 definition > > RFC ->v1: > - add a comment to explain the PMCEID0/1 splits > --- > arm/pmu.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++ > arm/unittests.cfg | 6 +++++ > 2 files changed, 68 insertions(+) > > diff --git a/arm/pmu.c b/arm/pmu.c > index d24857e..4a26a76 100644 > --- a/arm/pmu.c > +++ b/arm/pmu.c > @@ -101,6 +101,10 @@ static inline void precise_instrs_loop(int loop, uint32_t pmcr) > : [pmcr] "r" (pmcr), [z] "r" (0) > : "cc"); > } > + > +/* event counter tests only implemented for aarch64 */ > +static void test_event_introspection(void) {} > + > #elif defined(__aarch64__) > #define ID_AA64DFR0_PERFMON_SHIFT 8 > #define ID_AA64DFR0_PERFMON_MASK 0xf > @@ -139,6 +143,61 @@ static inline void precise_instrs_loop(int loop, uint32_t pmcr) > : [pmcr] "r" (pmcr) > : "cc"); > } > + > +#define PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) > + > +static bool is_event_supported(uint32_t n, bool warn) > +{ > + uint64_t pmceid0 = read_sysreg(pmceid0_el0); > + uint64_t pmceid1 = read_sysreg_s(PMCEID1_EL0); > + bool supported; > + uint64_t reg; > + > + /* > + * The low 32-bits of PMCEID0/1 respectly describe > + * event support for events 0-31/32-63. Their High > + * 32-bits describe support for extended events > + * starting at 0x4000, using the same split. > + */ > + if (n >= 0x0 && n <= 0x3F) > + reg = (pmceid0 & 0xFFFFFFFF) | ((pmceid1 & 0xFFFFFFFF) << 32); Maybe it's time to add #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) #define lower_32_bits(n) ((u32)(n)) to the kvm-unit-tests framework. > + else if (n >= 0x4000 && n <= 0x403F) > + reg = (pmceid0 >> 32) | ((pmceid1 >> 32) << 32); > + else > + abort(); assert(0) ensure we get a dump_stack() (although I haven't fixed dump_stack for arm64 yet...). Could also do the assert first assert((n >= 0x0 && n <= 0x3F) || (n >= 0x4000 && n <= 0x403F)) if (n <= 0x3F) ... else ... What about defines for these hex numbers? > + > + supported = reg & (1UL << (n & 0x3F)); ^ extra space > + > + if (!supported && warn) > + report_info("event %d is not supported", n); > + return supported; > +} > + > +static void test_event_introspection(void) > +{ > + bool required_events; > + > + if (!pmu.nb_implemented_counters) { > + report_skip("No event counter, skip ..."); > + return; > + } > + > + /* PMUv3 requires an implementation includes some common events */ > + required_events = is_event_supported(0x0, true) /* SW_INCR */ && > + is_event_supported(0x11, true) /* CPU_CYCLES */ && > + (is_event_supported(0x8, true) /* INST_RETIRED */ || > + is_event_supported(0x1B, true) /* INST_PREC */); If defines are created then the comments can go away required_events = is_event_supported(SW_INCR, true) && is_event_supported(CPU_CYCLES, true) && (is_event_supported(INST_RETIRED, true) || is_event_supported(INST_PREC, true)); > + > + if (pmu.version == 0x4) { > + /* ARMv8.1 PMU: STALL_FRONTEND and STALL_BACKEND are required */ > + required_events = required_events && > + is_event_supported(0x23, true) && > + is_event_supported(0x24, true); > + } > + > + report(required_events, "Check required events are implemented"); > +} > + > #endif > > /* > @@ -326,6 +385,9 @@ int main(int argc, char *argv[]) > "Monotonically increasing cycle count"); > report(check_cpi(cpi), "Cycle/instruction ratio"); > pmccntr64_test(); > + } else if (strcmp(argv[1], "event-introspection") == 0) { > + report_prefix_push(argv[1]); > + test_event_introspection(); prefix pop > } else { > report_abort("Unknown sub-test '%s'", argv[1]); > } > diff --git a/arm/unittests.cfg b/arm/unittests.cfg > index 79f0d7a..4433ef3 100644 > --- a/arm/unittests.cfg > +++ b/arm/unittests.cfg > @@ -66,6 +66,12 @@ file = pmu.flat > groups = pmu > extra_params = -append 'cycle-counter 0' > > +[pmu-event-introspection] > +file = pmu.flat > +groups = pmu > +arch = arm64 > +extra_params = -append 'event-introspection' > + > # Test PMU support (TCG) with -icount IPC=1 > #[pmu-tcg-icount-1] > #file = pmu.flat > -- > 2.20.1 > > Thanks, drew
diff --git a/arm/pmu.c b/arm/pmu.c index d24857e..4a26a76 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -101,6 +101,10 @@ static inline void precise_instrs_loop(int loop, uint32_t pmcr) : [pmcr] "r" (pmcr), [z] "r" (0) : "cc"); } + +/* event counter tests only implemented for aarch64 */ +static void test_event_introspection(void) {} + #elif defined(__aarch64__) #define ID_AA64DFR0_PERFMON_SHIFT 8 #define ID_AA64DFR0_PERFMON_MASK 0xf @@ -139,6 +143,61 @@ static inline void precise_instrs_loop(int loop, uint32_t pmcr) : [pmcr] "r" (pmcr) : "cc"); } + +#define PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) + +static bool is_event_supported(uint32_t n, bool warn) +{ + uint64_t pmceid0 = read_sysreg(pmceid0_el0); + uint64_t pmceid1 = read_sysreg_s(PMCEID1_EL0); + bool supported; + uint64_t reg; + + /* + * The low 32-bits of PMCEID0/1 respectly describe + * event support for events 0-31/32-63. Their High + * 32-bits describe support for extended events + * starting at 0x4000, using the same split. + */ + if (n >= 0x0 && n <= 0x3F) + reg = (pmceid0 & 0xFFFFFFFF) | ((pmceid1 & 0xFFFFFFFF) << 32); + else if (n >= 0x4000 && n <= 0x403F) + reg = (pmceid0 >> 32) | ((pmceid1 >> 32) << 32); + else + abort(); + + supported = reg & (1UL << (n & 0x3F)); + + if (!supported && warn) + report_info("event %d is not supported", n); + return supported; +} + +static void test_event_introspection(void) +{ + bool required_events; + + if (!pmu.nb_implemented_counters) { + report_skip("No event counter, skip ..."); + return; + } + + /* PMUv3 requires an implementation includes some common events */ + required_events = is_event_supported(0x0, true) /* SW_INCR */ && + is_event_supported(0x11, true) /* CPU_CYCLES */ && + (is_event_supported(0x8, true) /* INST_RETIRED */ || + is_event_supported(0x1B, true) /* INST_PREC */); + + if (pmu.version == 0x4) { + /* ARMv8.1 PMU: STALL_FRONTEND and STALL_BACKEND are required */ + required_events = required_events && + is_event_supported(0x23, true) && + is_event_supported(0x24, true); + } + + report(required_events, "Check required events are implemented"); +} + #endif /* @@ -326,6 +385,9 @@ int main(int argc, char *argv[]) "Monotonically increasing cycle count"); report(check_cpi(cpi), "Cycle/instruction ratio"); pmccntr64_test(); + } else if (strcmp(argv[1], "event-introspection") == 0) { + report_prefix_push(argv[1]); + test_event_introspection(); } else { report_abort("Unknown sub-test '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 79f0d7a..4433ef3 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -66,6 +66,12 @@ file = pmu.flat groups = pmu extra_params = -append 'cycle-counter 0' +[pmu-event-introspection] +file = pmu.flat +groups = pmu +arch = arm64 +extra_params = -append 'event-introspection' + # Test PMU support (TCG) with -icount IPC=1 #[pmu-tcg-icount-1] #file = pmu.flat
If event counters are implemented check the common events required by the PMUv3 are implemented. Some are unconditionally required (SW_INCR, CPU_CYCLES, either INST_RETIRED or INST_SPEC). Some others only are required if the implementation implements some other features. Check those wich are unconditionally required. This test currently fails on TCG as neither INST_RETIRED or INST_SPEC are supported. Signed-off-by: Eric Auger <eric.auger@redhat.com> --- v1 -> v2: - fix is_event_supported() - fix boolean condition for PMU v4 - fix PMCEID0 definition RFC ->v1: - add a comment to explain the PMCEID0/1 splits --- arm/pmu.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 6 +++++ 2 files changed, 68 insertions(+)