[for_v25,2/3] x86/msr: Fixup "Intel SGX Launch Control hardware bits"
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Message ID 20200201174940.20984-3-sean.j.christopherson@intel.com
State New
Headers show
Series
  • x86/sgx: Fix feature control rebase
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Commit Message

Sean Christopherson Feb. 1, 2020, 5:49 p.m. UTC
Fix the Feature Control MSR bit definition for SGX LC that got borked
during the rebase to the latest upstream.

Note, the name diverges from what was previously used in the SGX series.
The decision made by/with Boris was to follow the SDM names.

Fixes: 24670c2036be ("x86/cpufeatures: x86/msr: Intel SGX Launch Control hardware bits")
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
 arch/x86/include/asm/msr-index.h | 1 +
 1 file changed, 1 insertion(+)

Patch
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diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 3ddc6336aaa2..a0776c262820 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -564,6 +564,7 @@ 
 #define FEAT_CTL_LOCKED				BIT(0)
 #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX		BIT(1)
 #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX	BIT(2)
+#define FEAT_CTL_SGX_LC_ENABLED			BIT(17)
 #define FEAT_CTL_SGX_ENABLED			BIT(18)
 #define FEAT_CTL_LMCE_ENABLED			BIT(20)