| Message ID | 20200203032943.121178-3-aik@ozlabs.ru (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [qemu,v6,1/6] ppc: Start CPU in the default mode which is big-endian 32bit | expand |
Alexey Kardashevskiy <aik@ozlabs.ru> writes: > At the moment "pseries" starts in SLOF which only expects the FDT blob > pointer in r3. As we are going to introduce a OpenFirmware support in > QEMU, we will be booting OF clients directly and these expect a stack > pointer in r1, the OF entry point in r5 and in addition to this, Linux > looks at r3/r4 for the initramdisk location (although vmlinux can find > this from the device tree but zImage from distro kernels cannot). > > This extends spapr_cpu_set_entry_state() to take more registers. This > should cause no behavioral change. > > Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> > --- > include/hw/ppc/spapr_cpu_core.h | 4 +++- > hw/ppc/spapr.c | 4 ++-- > hw/ppc/spapr_cpu_core.c | 7 ++++++- > hw/ppc/spapr_rtas.c | 2 +- > 4 files changed, 12 insertions(+), 5 deletions(-) > > diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h > index 1c4cc6559c52..edd7214fafcf 100644 > --- a/include/hw/ppc/spapr_cpu_core.h > +++ b/include/hw/ppc/spapr_cpu_core.h > @@ -40,7 +40,9 @@ typedef struct SpaprCpuCoreClass { > } SpaprCpuCoreClass; > > const char *spapr_get_cpu_core_type(const char *cpu_type); > -void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3); > +void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, > + target_ulong r1, target_ulong r3, > + target_ulong r4, target_ulong r5); > > typedef struct SpaprCpuState { > uint64_t vpa_addr; > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index c9b2e0a5e060..660a4b60e072 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -1674,8 +1674,8 @@ static void spapr_machine_reset(MachineState *machine) > spapr->fdt_blob = fdt; > > /* Set up the entry state */ > - spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); > - first_ppc_cpu->env.gpr[5] = 0; > + spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, > + 0, fdt_addr, 0, 0); > > spapr->cas_reboot = false; > > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c > index d09125d9afd4..696b76598dd7 100644 > --- a/hw/ppc/spapr_cpu_core.c > +++ b/hw/ppc/spapr_cpu_core.c > @@ -84,13 +84,18 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu) > spapr_irq_cpu_intc_reset(spapr, cpu); > } > > -void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3) > +void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, > + target_ulong r1, target_ulong r3, > + target_ulong r4, target_ulong r5) > { > PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); > CPUPPCState *env = &cpu->env; > > env->nip = nip; > + env->gpr[1] = r1; > env->gpr[3] = r3; > + env->gpr[4] = r4; > + env->gpr[5] = r5; > kvmppc_set_reg_ppc_online(cpu, 1); > CPU(cpu)->halted = 0; > /* Enable Power-saving mode Exit Cause exceptions */ > diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c > index 656fdd221665..9e3cbd70bbd9 100644 > --- a/hw/ppc/spapr_rtas.c > +++ b/hw/ppc/spapr_rtas.c > @@ -190,7 +190,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr, > */ > newcpu->env.tb_env->tb_offset = callcpu->env.tb_env->tb_offset; > > - spapr_cpu_set_entry_state(newcpu, start, r3); > + spapr_cpu_set_entry_state(newcpu, start, 0, r3, 0, 0); > > qemu_cpu_kick(CPU(newcpu));
On Mon, 3 Feb 2020 14:29:39 +1100 Alexey Kardashevskiy <aik@ozlabs.ru> wrote: > At the moment "pseries" starts in SLOF which only expects the FDT blob > pointer in r3. As we are going to introduce a OpenFirmware support in > QEMU, we will be booting OF clients directly and these expect a stack > pointer in r1, the OF entry point in r5 and in addition to this, Linux > looks at r3/r4 for the initramdisk location (although vmlinux can find > this from the device tree but zImage from distro kernels cannot). > > This extends spapr_cpu_set_entry_state() to take more registers. This > should cause no behavioral change. > > Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> > --- Reviewed-by: Greg Kurz <groug@kaod.org> > include/hw/ppc/spapr_cpu_core.h | 4 +++- > hw/ppc/spapr.c | 4 ++-- > hw/ppc/spapr_cpu_core.c | 7 ++++++- > hw/ppc/spapr_rtas.c | 2 +- > 4 files changed, 12 insertions(+), 5 deletions(-) > > diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h > index 1c4cc6559c52..edd7214fafcf 100644 > --- a/include/hw/ppc/spapr_cpu_core.h > +++ b/include/hw/ppc/spapr_cpu_core.h > @@ -40,7 +40,9 @@ typedef struct SpaprCpuCoreClass { > } SpaprCpuCoreClass; > > const char *spapr_get_cpu_core_type(const char *cpu_type); > -void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3); > +void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, > + target_ulong r1, target_ulong r3, > + target_ulong r4, target_ulong r5); > > typedef struct SpaprCpuState { > uint64_t vpa_addr; > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index c9b2e0a5e060..660a4b60e072 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -1674,8 +1674,8 @@ static void spapr_machine_reset(MachineState *machine) > spapr->fdt_blob = fdt; > > /* Set up the entry state */ > - spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); > - first_ppc_cpu->env.gpr[5] = 0; > + spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, > + 0, fdt_addr, 0, 0); > > spapr->cas_reboot = false; > > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c > index d09125d9afd4..696b76598dd7 100644 > --- a/hw/ppc/spapr_cpu_core.c > +++ b/hw/ppc/spapr_cpu_core.c > @@ -84,13 +84,18 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu) > spapr_irq_cpu_intc_reset(spapr, cpu); > } > > -void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3) > +void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, > + target_ulong r1, target_ulong r3, > + target_ulong r4, target_ulong r5) > { > PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); > CPUPPCState *env = &cpu->env; > > env->nip = nip; > + env->gpr[1] = r1; > env->gpr[3] = r3; > + env->gpr[4] = r4; > + env->gpr[5] = r5; > kvmppc_set_reg_ppc_online(cpu, 1); > CPU(cpu)->halted = 0; > /* Enable Power-saving mode Exit Cause exceptions */ > diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c > index 656fdd221665..9e3cbd70bbd9 100644 > --- a/hw/ppc/spapr_rtas.c > +++ b/hw/ppc/spapr_rtas.c > @@ -190,7 +190,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr, > */ > newcpu->env.tb_env->tb_offset = callcpu->env.tb_env->tb_offset; > > - spapr_cpu_set_entry_state(newcpu, start, r3); > + spapr_cpu_set_entry_state(newcpu, start, 0, r3, 0, 0); > > qemu_cpu_kick(CPU(newcpu)); >
diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h index 1c4cc6559c52..edd7214fafcf 100644 --- a/include/hw/ppc/spapr_cpu_core.h +++ b/include/hw/ppc/spapr_cpu_core.h @@ -40,7 +40,9 @@ typedef struct SpaprCpuCoreClass { } SpaprCpuCoreClass; const char *spapr_get_cpu_core_type(const char *cpu_type); -void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3); +void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, + target_ulong r1, target_ulong r3, + target_ulong r4, target_ulong r5); typedef struct SpaprCpuState { uint64_t vpa_addr; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index c9b2e0a5e060..660a4b60e072 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1674,8 +1674,8 @@ static void spapr_machine_reset(MachineState *machine) spapr->fdt_blob = fdt; /* Set up the entry state */ - spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); - first_ppc_cpu->env.gpr[5] = 0; + spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, + 0, fdt_addr, 0, 0); spapr->cas_reboot = false; diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index d09125d9afd4..696b76598dd7 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -84,13 +84,18 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu) spapr_irq_cpu_intc_reset(spapr, cpu); } -void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3) +void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, + target_ulong r1, target_ulong r3, + target_ulong r4, target_ulong r5) { PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env = &cpu->env; env->nip = nip; + env->gpr[1] = r1; env->gpr[3] = r3; + env->gpr[4] = r4; + env->gpr[5] = r5; kvmppc_set_reg_ppc_online(cpu, 1); CPU(cpu)->halted = 0; /* Enable Power-saving mode Exit Cause exceptions */ diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 656fdd221665..9e3cbd70bbd9 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -190,7 +190,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr, */ newcpu->env.tb_env->tb_offset = callcpu->env.tb_env->tb_offset; - spapr_cpu_set_entry_state(newcpu, start, r3); + spapr_cpu_set_entry_state(newcpu, start, 0, r3, 0, 0); qemu_cpu_kick(CPU(newcpu));
At the moment "pseries" starts in SLOF which only expects the FDT blob pointer in r3. As we are going to introduce a OpenFirmware support in QEMU, we will be booting OF clients directly and these expect a stack pointer in r1, the OF entry point in r5 and in addition to this, Linux looks at r3/r4 for the initramdisk location (although vmlinux can find this from the device tree but zImage from distro kernels cannot). This extends spapr_cpu_set_entry_state() to take more registers. This should cause no behavioral change. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> --- include/hw/ppc/spapr_cpu_core.h | 4 +++- hw/ppc/spapr.c | 4 ++-- hw/ppc/spapr_cpu_core.c | 7 ++++++- hw/ppc/spapr_rtas.c | 2 +- 4 files changed, 12 insertions(+), 5 deletions(-)