| Message ID | 20200204112927.17391-8-anshuman.gupta@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | 3 display pipes combination system support | expand |
On Tue, Feb 04, 2020 at 04:59:27PM +0530, Anshuman Gupta wrote: > Allow 3-display pipes SKU system with any combination > in INTEL_INFO pipe mask. > B.Spec:50075 > > changes since RFC: > - using intel_pipe_mask_is_valid() function to check integrity of > pipe_mask. [Ville] > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > --- > drivers/gpu/drm/i915/intel_device_info.c | 38 +++++++++++++++++------- > 1 file changed, 28 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index fcdacd6d4aa5..caf93a68a056 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -896,6 +896,30 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915) > RUNTIME_INFO(i915)->platform_mask[pi] |= mask; > } > > +static bool > +intel_pipe_mask_is_valid(struct drm_i915_private *dev_priv, u8 pipe_mask) > +{ > + /* > + * At least one pipe should be enabled. > + */ > + if (pipe_mask == 0) > + return false; Doesn't that just mean the entire display engine is fused off? > + /* > + * if there are disabled pipes they should be the last ones, > + * with no holses in the mask for Dispaly Gen<=12. "holes" > + */ > + if (!is_power_of_2(pipe_mask + 1)) { > + if (INTEL_GEN(dev_priv) <= 11) > + return false; > + else if (IS_TIGERLAKE(dev_priv)) > + return false; > + else if (IS_GEN(dev_priv, 12)) > + return true; Why is tgl and rest of gen12 treated differently? I thought this flexible fusing thing was next-gen stuff. The structure of this function is a bit wonky. Simpler: intel_pipe_mask_is_valid() { if (is_whatever_supports_holes) return true; return is_power_of_2(); } > + } > + > + return true; > +} > + > /** > * intel_device_info_runtime_init - initialize runtime info > * @dev_priv: the i915 device > @@ -995,17 +1019,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) > (dfsm & TGL_DFSM_PIPE_D_DISABLE)) > enabled_mask &= ~BIT(PIPE_D); > > - /* > - * At least one pipe should be enabled and if there are > - * disabled pipes, they should be the last ones, with no holes > - * in the mask. > - */ > - if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1)) > - drm_err(&dev_priv->drm, > - "invalid pipe fuse configuration: enabled_mask=0x%x\n", > - enabled_mask); > - else > + if (intel_pipe_mask_is_valid(dev_priv, enabled_mask)) > info->pipe_mask = enabled_mask; > + else > + drm_err(&dev_priv->drm, "invalid pipe fuse configuration: enabled_mask=0x%x\n", > + enabled_mask); > > if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) > info->display.has_hdcp = 0; > -- > 2.24.0
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index fcdacd6d4aa5..caf93a68a056 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -896,6 +896,30 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915) RUNTIME_INFO(i915)->platform_mask[pi] |= mask; } +static bool +intel_pipe_mask_is_valid(struct drm_i915_private *dev_priv, u8 pipe_mask) +{ + /* + * At least one pipe should be enabled. + */ + if (pipe_mask == 0) + return false; + /* + * if there are disabled pipes they should be the last ones, + * with no holses in the mask for Dispaly Gen<=12. + */ + if (!is_power_of_2(pipe_mask + 1)) { + if (INTEL_GEN(dev_priv) <= 11) + return false; + else if (IS_TIGERLAKE(dev_priv)) + return false; + else if (IS_GEN(dev_priv, 12)) + return true; + } + + return true; +} + /** * intel_device_info_runtime_init - initialize runtime info * @dev_priv: the i915 device @@ -995,17 +1019,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) (dfsm & TGL_DFSM_PIPE_D_DISABLE)) enabled_mask &= ~BIT(PIPE_D); - /* - * At least one pipe should be enabled and if there are - * disabled pipes, they should be the last ones, with no holes - * in the mask. - */ - if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1)) - drm_err(&dev_priv->drm, - "invalid pipe fuse configuration: enabled_mask=0x%x\n", - enabled_mask); - else + if (intel_pipe_mask_is_valid(dev_priv, enabled_mask)) info->pipe_mask = enabled_mask; + else + drm_err(&dev_priv->drm, "invalid pipe fuse configuration: enabled_mask=0x%x\n", + enabled_mask); if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) info->display.has_hdcp = 0;
Allow 3-display pipes SKU system with any combination in INTEL_INFO pipe mask. B.Spec:50075 changes since RFC: - using intel_pipe_mask_is_valid() function to check integrity of pipe_mask. [Ville] Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/intel_device_info.c | 38 +++++++++++++++++------- 1 file changed, 28 insertions(+), 10 deletions(-)