@@ -680,6 +680,18 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
return 0;
}
+static void
+gen6_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ wa_write_or(wal, GEN6_MBCTL, GEN6_MBCTL_ENABLE_BOOT_FETCH);
+}
+
+static void
+gen7_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ wa_write_or(wal, GEN6_MBCTL, GEN6_MBCTL_ENABLE_BOOT_FETCH);
+}
+
static void
gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
@@ -962,7 +974,11 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
bxt_gt_workarounds_init(i915, wal);
else if (IS_SKYLAKE(i915))
skl_gt_workarounds_init(i915, wal);
- else if (INTEL_GEN(i915) <= 8)
+ else if (IS_GEN(i915, 7))
+ gen7_gt_workarounds_init(i915, wal);
+ else if (IS_GEN(i915, 6))
+ gen6_gt_workarounds_init(i915, wal);
+ else if (INTEL_GEN(i915) < 6)
return;
else
MISSING_CASE(INTEL_GEN(i915));
Mika spotted that we should be setting BIT(4) of MBCTL prior to execution. "The driver must set this bit in the following scenarios: - To reload the HW boot context every time it gets loaded through the OS. - After an FLR clears the register (the BIOS won’t run afterwards)." Make it so. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)