| Message ID | 20200214181547.21408-14-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/arm: vfp feature and decodetree cleanup | expand |
On Fri, 14 Feb 2020 at 18:16, Richard Henderson <richard.henderson@linaro.org> wrote: > > Now that we no longer have an early check for ARM_FEATURE_VFP, > we can use the proper ISA check in trans_VLLDM_VLSTM. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/vfp.decode | 2 ++ > target/arm/translate-vfp.inc.c | 35 ++++++++++++++++++++++ > target/arm/translate.c | 53 ++++++---------------------------- > 3 files changed, 46 insertions(+), 44 deletions(-) > > diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode > index a67b3f29ee..592fe9e1e4 100644 > --- a/target/arm/vfp.decode > +++ b/target/arm/vfp.decode > @@ -242,3 +242,5 @@ VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \ > vd=%vd_sp vm=%vm_sp > VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \ > vd=%vd_sp vm=%vm_dp > + > +VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 > diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c > index f6f7601fe2..8f2b97e0e7 100644 > --- a/target/arm/translate-vfp.inc.c > +++ b/target/arm/translate-vfp.inc.c > @@ -2816,3 +2816,38 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) > tcg_temp_free_ptr(fpst); > return true; > } > + > +/* > + * Decode VLLDM of VLSTM are nonstandard because: "Decode of VLLDM and VLSTM" > + * * if there is no FPU then these insns must NOP in > + * Secure state and UNDEF in Nonsecure state > + * * if there is an FPU then these insns do not have > + * the usual behaviour that disas_vfp_insn() provides of > + * being controlled by CPACR/NSACR enable bits or the > + * lazy-stacking logic. s/disas_vfp_insn/vfp_access_check/ (we never updated this old comment when we moved the logic as part of the decodetree conversion). > + */ > +static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) > +{ > + TCGv_i32 fptr; > + > + if (!arm_dc_feature(s, ARM_FEATURE_M) || > + !arm_dc_feature(s, ARM_FEATURE_V8)) { > + return false; > + } > + if (!dc_isar_feature(aa32_fpsp_v2, s)) { > + /* No FPU: NOP if secure, otherwise UNDEF. */ > + return s->v8m_secure; > + } We need to UNDEF if !v8m_secure even if there is an FPU. > + > + fptr = load_reg(s, a->rn); > + if (a->l) { > + gen_helper_v7m_vlldm(cpu_env, fptr); > + } else { > + gen_helper_v7m_vlstm(cpu_env, fptr); > + } > + tcg_temp_free_i32(fptr); > + > + /* End the TB, because we have updated FP control bits */ > + s->base.is_jmp = DISAS_UPDATE; > + return true; > +} thanks -- PMM
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index a67b3f29ee..592fe9e1e4 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -242,3 +242,5 @@ VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \ vd=%vd_sp vm=%vm_sp VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \ vd=%vd_sp vm=%vm_dp + +VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index f6f7601fe2..8f2b97e0e7 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -2816,3 +2816,38 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) tcg_temp_free_ptr(fpst); return true; } + +/* + * Decode VLLDM of VLSTM are nonstandard because: + * * if there is no FPU then these insns must NOP in + * Secure state and UNDEF in Nonsecure state + * * if there is an FPU then these insns do not have + * the usual behaviour that disas_vfp_insn() provides of + * being controlled by CPACR/NSACR enable bits or the + * lazy-stacking logic. + */ +static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) +{ + TCGv_i32 fptr; + + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + /* No FPU: NOP if secure, otherwise UNDEF. */ + return s->v8m_secure; + } + + fptr = load_reg(s, a->rn); + if (a->l) { + gen_helper_v7m_vlldm(cpu_env, fptr); + } else { + gen_helper_v7m_vlstm(cpu_env, fptr); + } + tcg_temp_free_i32(fptr); + + /* End the TB, because we have updated FP control bits */ + s->base.is_jmp = DISAS_UPDATE; + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index e8c3d4f26f..b2641b4262 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10708,53 +10708,18 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; /* op0 = 0b11 : unallocated */ } - /* - * Decode VLLDM and VLSTM first: these are nonstandard because: - * * if there is no FPU then these insns must NOP in - * Secure state and UNDEF in Nonsecure state - * * if there is an FPU then these insns do not have - * the usual behaviour that disas_vfp_insn() provides of - * being controlled by CPACR/NSACR enable bits or the - * lazy-stacking logic. - */ - if (arm_dc_feature(s, ARM_FEATURE_V8) && - (insn & 0xffa00f00) == 0xec200a00) { - /* 0b1110_1100_0x1x_xxxx_xxxx_1010_xxxx_xxxx - * - VLLDM, VLSTM - * We choose to UNDEF if the RAZ bits are non-zero. - */ - if (!s->v8m_secure || (insn & 0x0040f0ff)) { + if (disas_vfp_insn(s, insn)) { + if (((insn >> 8) & 0xe) == 10 && + dc_isar_feature(aa32_fpsp_v2, s)) { + /* FP, and the CPU supports it */ goto illegal_op; + } else { + /* All other insns: NOCP */ + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), + default_exception_el(s)); } - - if (arm_dc_feature(s, ARM_FEATURE_VFP)) { - uint32_t rn = (insn >> 16) & 0xf; - TCGv_i32 fptr = load_reg(s, rn); - - if (extract32(insn, 20, 1)) { - gen_helper_v7m_vlldm(cpu_env, fptr); - } else { - gen_helper_v7m_vlstm(cpu_env, fptr); - } - tcg_temp_free_i32(fptr); - - /* End the TB, because we have updated FP control bits */ - s->base.is_jmp = DISAS_UPDATE; - } - break; } - if (arm_dc_feature(s, ARM_FEATURE_VFP) && - ((insn >> 8) & 0xe) == 10) { - /* FP, and the CPU supports it */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - break; - } - - /* All other insns: NOCP */ - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(), - default_exception_el(s)); break; } if ((insn & 0xfe000a00) == 0xfc000800
Now that we no longer have an early check for ARM_FEATURE_VFP, we can use the proper ISA check in trans_VLLDM_VLSTM. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/vfp.decode | 2 ++ target/arm/translate-vfp.inc.c | 35 ++++++++++++++++++++++ target/arm/translate.c | 53 ++++++---------------------------- 3 files changed, 46 insertions(+), 44 deletions(-)