| Message ID | 20200218133019.22299-5-geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 721b76195b31467e56851fbab3855e700f281270 |
| Headers | show |
| Series | arm: dts: renesas: Add reset control properties for display | expand |
> On February 18, 2020 at 2:30 PM Geert Uytterhoeven <geert+renesas@glider.be> wrote: > > > Add reset control properties to the device nodes for the Display Units > on all supported RZ/G2 SoCs. Note that on these SoCs, there is only a > single reset for each pair of DU channels. > > Join the clocks lines while at it, to increase uniformity. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> FTR: I can't review this one, I don't have the datasheet. CU Uli
Hi Geert, Thank you for the patch. On Tue, Feb 18, 2020 at 02:30:19PM +0100, Geert Uytterhoeven wrote: > Add reset control properties to the device nodes for the Display Units > on all supported RZ/G2 SoCs. Note that on these SoCs, there is only a > single reset for each pair of DU channels. > > Join the clocks lines while at it, to increase uniformity. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > v2: > - New. > --- > arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 5 +++-- > arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 5 +++-- > arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 5 +++-- > 3 files changed, 9 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi > index 507e78ebaab52330..79023433a740b7ca 100644 > --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi > @@ -2634,10 +2634,11 @@ > interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&cpg CPG_MOD 724>, > - <&cpg CPG_MOD 723>, > + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, > <&cpg CPG_MOD 722>; > clock-names = "du.0", "du.1", "du.2"; > + resets = <&cpg 724>, <&cpg 722>; > + reset-names = "du.0", "du.2"; > status = "disabled"; > > renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; > diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi > index 93dd10b5d6d05712..3137f735974be165 100644 > --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi > @@ -2480,10 +2480,11 @@ > interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&cpg CPG_MOD 724>, > - <&cpg CPG_MOD 723>, > + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, > <&cpg CPG_MOD 721>; > clock-names = "du.0", "du.1", "du.3"; > + resets = <&cpg 724>, <&cpg 722>; > + reset-names = "du.0", "du.3"; Same as for 3/4, I wonder if this should be "du.2". Otherwise the patch looks fine. > status = "disabled"; > > renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > index d4eee8fef35da74e..22785cbddff5d08c 100644 > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > @@ -1810,9 +1810,10 @@ > reg = <0 0xfeb00000 0 0x40000>; > interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&cpg CPG_MOD 724>, > - <&cpg CPG_MOD 723>; > + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; > clock-names = "du.0", "du.1"; > + resets = <&cpg 724>; > + reset-names = "du.0"; > renesas,vsps = <&vspd0 0>, <&vspd1 0>; > > status = "disabled";
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 507e78ebaab52330..79023433a740b7ca 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2634,10 +2634,11 @@ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>; clock-names = "du.0", "du.1", "du.2"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.2"; status = "disabled"; renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 93dd10b5d6d05712..3137f735974be165 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2480,10 +2480,11 @@ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 721>; clock-names = "du.0", "du.1", "du.3"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.3"; status = "disabled"; renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index d4eee8fef35da74e..22785cbddff5d08c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1810,9 +1810,10 @@ reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; renesas,vsps = <&vspd0 0>, <&vspd1 0>; status = "disabled";
Add reset control properties to the device nodes for the Display Units on all supported RZ/G2 SoCs. Note that on these SoCs, there is only a single reset for each pair of DU channels. Join the clocks lines while at it, to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v2: - New. --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 5 +++-- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 5 +++-- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 5 +++-- 3 files changed, 9 insertions(+), 6 deletions(-)