| Message ID | 20200218133019.22299-3-geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 9e1232631d4e8e30096fa758a0e1fb9e08f219f9 |
| Headers | show |
| Series | arm: dts: renesas: Add reset control properties for display | expand |
> On February 18, 2020 at 2:30 PM Geert Uytterhoeven <geert+renesas@glider.be> wrote: > > > Add reset control properties to the devices node for the Display Units > on all supported RZ/G1 SoCs. Note that on these SoCs, there is only a > single reset for all DU channels. > > Join the clocks lines while at it, to increase uniformity. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > v2: > - New. > --- > arch/arm/boot/dts/r8a7743.dtsi | 5 +++-- > arch/arm/boot/dts/r8a7744.dtsi | 5 +++-- > arch/arm/boot/dts/r8a7745.dtsi | 2 ++ > arch/arm/boot/dts/r8a77470.dtsi | 5 +++-- > 4 files changed, 11 insertions(+), 6 deletions(-) > > diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi > index 1cd19a569bd0fb66..e8b340bb99bc3031 100644 > --- a/arch/arm/boot/dts/r8a7743.dtsi > +++ b/arch/arm/boot/dts/r8a7743.dtsi > @@ -1669,9 +1669,10 @@ > reg = <0 0xfeb00000 0 0x40000>; > interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&cpg CPG_MOD 724>, > - <&cpg CPG_MOD 723>; > + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; > clock-names = "du.0", "du.1"; > + resets = <&cpg 724>; > + reset-names = "du.0"; > status = "disabled"; > > ports { > diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi > index 1c82dd0abd76c4c9..def840b8b2d3c0c4 100644 > --- a/arch/arm/boot/dts/r8a7744.dtsi > +++ b/arch/arm/boot/dts/r8a7744.dtsi > @@ -1655,9 +1655,10 @@ > reg = <0 0xfeb00000 0 0x40000>; > interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&cpg CPG_MOD 724>, > - <&cpg CPG_MOD 723>; > + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; > clock-names = "du.0", "du.1"; > + resets = <&cpg 724>; > + reset-names = "du.0"; > status = "disabled"; > > ports { > diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi > index 3b413658eb8d8fac..7ab58d8bb74010d6 100644 > --- a/arch/arm/boot/dts/r8a7745.dtsi > +++ b/arch/arm/boot/dts/r8a7745.dtsi > @@ -1510,6 +1510,8 @@ > <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; > clock-names = "du.0", "du.1"; > + resets = <&cpg 724>; > + reset-names = "du.0"; > status = "disabled"; > > ports { > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi > index 6efcef1670e15a95..f5515319227609a4 100644 > --- a/arch/arm/boot/dts/r8a77470.dtsi > +++ b/arch/arm/boot/dts/r8a77470.dtsi > @@ -942,9 +942,10 @@ > reg = <0 0xfeb00000 0 0x40000>; > interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&cpg CPG_MOD 724>, > - <&cpg CPG_MOD 723>; > + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; > clock-names = "du.0", "du.1"; > + resets = <&cpg 724>; > + reset-names = "du.0"; > status = "disabled"; > > ports { > -- > 2.17.1 > Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu> CU Uli
Hi Geert, Thank you for the patch. On Tue, Feb 18, 2020 at 02:30:17PM +0100, Geert Uytterhoeven wrote: > Add reset control properties to the devices node for the Display Units > on all supported RZ/G1 SoCs. Note that on these SoCs, there is only a > single reset for all DU channels. > > Join the clocks lines while at it, to increase uniformity. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > v2: > - New. > --- > arch/arm/boot/dts/r8a7743.dtsi | 5 +++-- > arch/arm/boot/dts/r8a7744.dtsi | 5 +++-- > arch/arm/boot/dts/r8a7745.dtsi | 2 ++ > arch/arm/boot/dts/r8a77470.dtsi | 5 +++-- > 4 files changed, 11 insertions(+), 6 deletions(-) > > diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi > index 1cd19a569bd0fb66..e8b340bb99bc3031 100644 > --- a/arch/arm/boot/dts/r8a7743.dtsi > +++ b/arch/arm/boot/dts/r8a7743.dtsi > @@ -1669,9 +1669,10 @@ > reg = <0 0xfeb00000 0 0x40000>; > interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&cpg CPG_MOD 724>, > - <&cpg CPG_MOD 723>; > + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; > clock-names = "du.0", "du.1"; > + resets = <&cpg 724>; > + reset-names = "du.0"; Same comment as for 1/4. > status = "disabled"; > > ports { > diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi > index 1c82dd0abd76c4c9..def840b8b2d3c0c4 100644 > --- a/arch/arm/boot/dts/r8a7744.dtsi > +++ b/arch/arm/boot/dts/r8a7744.dtsi > @@ -1655,9 +1655,10 @@ > reg = <0 0xfeb00000 0 0x40000>; > interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&cpg CPG_MOD 724>, > - <&cpg CPG_MOD 723>; > + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; > clock-names = "du.0", "du.1"; > + resets = <&cpg 724>; > + reset-names = "du.0"; > status = "disabled"; > > ports { > diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi > index 3b413658eb8d8fac..7ab58d8bb74010d6 100644 > --- a/arch/arm/boot/dts/r8a7745.dtsi > +++ b/arch/arm/boot/dts/r8a7745.dtsi > @@ -1510,6 +1510,8 @@ > <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; > clock-names = "du.0", "du.1"; > + resets = <&cpg 724>; > + reset-names = "du.0"; > status = "disabled"; > > ports { > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi > index 6efcef1670e15a95..f5515319227609a4 100644 > --- a/arch/arm/boot/dts/r8a77470.dtsi > +++ b/arch/arm/boot/dts/r8a77470.dtsi > @@ -942,9 +942,10 @@ > reg = <0 0xfeb00000 0 0x40000>; > interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&cpg CPG_MOD 724>, > - <&cpg CPG_MOD 723>; > + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; > clock-names = "du.0", "du.1"; > + resets = <&cpg 724>; > + reset-names = "du.0"; > status = "disabled"; > > ports {
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 1cd19a569bd0fb66..e8b340bb99bc3031 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -1669,9 +1669,10 @@ reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; status = "disabled"; ports { diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 1c82dd0abd76c4c9..def840b8b2d3c0c4 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -1655,9 +1655,10 @@ reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; status = "disabled"; ports { diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 3b413658eb8d8fac..7ab58d8bb74010d6 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -1510,6 +1510,8 @@ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; status = "disabled"; ports { diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 6efcef1670e15a95..f5515319227609a4 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -942,9 +942,10 @@ reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; status = "disabled"; ports {
Add reset control properties to the devices node for the Display Units on all supported RZ/G1 SoCs. Note that on these SoCs, there is only a single reset for all DU channels. Join the clocks lines while at it, to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v2: - New. --- arch/arm/boot/dts/r8a7743.dtsi | 5 +++-- arch/arm/boot/dts/r8a7744.dtsi | 5 +++-- arch/arm/boot/dts/r8a7745.dtsi | 2 ++ arch/arm/boot/dts/r8a77470.dtsi | 5 +++-- 4 files changed, 11 insertions(+), 6 deletions(-)