[CI,03/10] drm/i915/guc: Kill USES_GUC_SUBMISSION macro

Message ID	20200218223327.11058-3-daniele.ceraolospurio@intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=zVty=4G=lists.freedesktop.org=intel-gfx-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6D1BB24125 From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> To: intel-gfx@lists.freedesktop.org Date: Tue, 18 Feb 2020 14:33:20 -0800 Message-Id: <20200218223327.11058-3-daniele.ceraolospurio@intel.com> In-Reply-To: <20200218223327.11058-1-daniele.ceraolospurio@intel.com> References: <20200218223327.11058-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [CI 03/10] drm/i915/guc: Kill USES_GUC_SUBMISSION macro Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	[CI,01/10] drm/i915/debugfs: Pass guc_log struct to i915_guc_log_info \| expand [CI,01/10] drm/i915/debugfs: Pass guc_log struct to i915_guc_log_info [CI,02/10] drm/i915/guc: Kill USES_GUC macro [CI,03/10] drm/i915/guc: Kill USES_GUC_SUBMISSION macro [CI,04/10] drm/i915/uc: Update the FW status on injected fetch error [CI,05/10] drm/i915/uc: autogenerate uC checker functions [CI,06/10] drm/i915/uc: Improve tracking of uC init status [CI,07/10] drm/i915/guc: Apply new uC status tracking to GuC submission as well [CI,08/10] drm/i915/uc: Abort early on uc_init failure [CI,09/10] drm/i915/uc: consolidate firmware cleanup [CI,10/10] HAX: drm/i915: default to enable_guc=2

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 3e82739bdbc0..adcebf22a3d3 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -1390,7 +1390,7 @@ set_engines__load_balance(struct i915_user_extension __user *base, void *data) if (!HAS_EXECLISTS(i915)) return -ENODEV; - if (USES_GUC_SUBMISSION(i915)) + if (intel_uc_uses_guc_submission(&i915->gt.uc)) return -ENODEV; /* not implement yet */ if (get_user(idx, &ext->engine_index)) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 3e5e6c86e843..c3514ec7b8db 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1640,7 +1640,7 @@ static int igt_reset_engines_atomic(void *arg) if (!intel_has_reset_engine(gt)) return 0; - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(&gt->uc)) return 0; igt_global_reset_lock(gt); diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index a9c9cfb2def8..6d69d51a2879 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -2109,7 +2109,7 @@ static int live_suppress_self_preempt(void *arg) if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915)) return 0; - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(&gt->uc)) return 0; /* presume black blox */ if (intel_vgpu_active(gt->i915)) @@ -3224,7 +3224,7 @@ static int live_virtual_engine(void *arg) unsigned int class, inst; int err; - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(&gt->uc)) return 0; for_each_engine(engine, gt, id) { @@ -3357,7 +3357,7 @@ static int live_virtual_mask(void *arg) unsigned int class, inst; int err; - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(&gt->uc)) return 0; for (class = 0; class <= MAX_ENGINE_CLASS; class++) { @@ -3499,7 +3499,7 @@ static int live_virtual_preserved(void *arg) * are preserved. */ - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(&gt->uc)) return 0; /* As we use CS_GPR we cannot run before they existed on all engines. */ @@ -3729,7 +3729,7 @@ static int live_virtual_bond(void *arg) unsigned int class, inst; int err; - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(&gt->uc)) return 0; for (class = 0; class <= MAX_ENGINE_CLASS; class++) { @@ -3890,7 +3890,7 @@ static int live_virtual_reset(void *arg) * forgotten. */ - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(&gt->uc)) return 0; if (!intel_has_reset_engine(gt)) diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c index 6ad6aca315f6..35406ecdf0b2 100644 --- a/drivers/gpu/drm/i915/gt/selftest_reset.c +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c @@ -115,7 +115,7 @@ static int igt_atomic_engine_reset(void *arg) if (!intel_has_reset_engine(gt)) return 0; - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(&gt->uc)) return 0; intel_gt_pm_get(gt); diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 685d1e04a5ff..5fe00ee6bd1b 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -1246,7 +1246,8 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu) ce->vm = i915_vm_get(&ppgtt->vm); intel_context_set_single_submission(ce); - if (!USES_GUC_SUBMISSION(i915)) { /* Max ring buffer size */ + /* Max ring buffer size */ + if (!intel_uc_uses_guc_submission(&engine->gt->uc)) { const unsigned int ring_size = 512 * SZ_4K; ce->ring = __intel_context_ring_size(ring_size); diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 81b3851ddca2..8f2525e4ce0f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1573,11 +1573,11 @@ static int i915_guc_info(struct seq_file *m, void *data) static int i915_guc_stage_pool(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); - const struct intel_guc *guc = &dev_priv->gt.uc.guc; - struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr; + struct intel_uc *uc = &dev_priv->gt.uc; + struct guc_stage_desc *desc = uc->guc.stage_desc_pool_vaddr; int index; - if (!USES_GUC_SUBMISSION(dev_priv)) + if (!intel_uc_uses_guc_submission(uc)) return -ENODEV; for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) { diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fb397a52ed33..198e63f3c776 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1693,9 +1693,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) -/* Having GuC is not the same as using GuC */ -#define USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc) - #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c index 38ebd5562c7c..5c189bc31da5 100644 --- a/drivers/gpu/drm/i915/intel_gvt.c +++ b/drivers/gpu/drm/i915/intel_gvt.c @@ -105,7 +105,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv) return 0; } - if (USES_GUC_SUBMISSION(dev_priv)) { + if (intel_uc_uses_guc_submission(&dev_priv->gt.uc)) { drm_err(&dev_priv->drm, "i915 GVT-g loading failed due to Graphics virtualization is not yet supported with GuC submission\n"); return -EIO;

[CI,03/10] drm/i915/guc: Kill USES_GUC_SUBMISSION macro

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