| Message ID | 20200220162758.13524-3-narmstrong@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/meson: add support for Amlogic Video FBC | expand |
Le 20/02/2020 à 17:27, Neil Armstrong a écrit : > Add the registers of the VPU VD1 Amlogic FBC decoder module, and routing > register. > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > drivers/gpu/drm/meson/meson_registers.h | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h > index 8ea00546cd4e..f784d7d1fe2e 100644 > --- a/drivers/gpu/drm/meson/meson_registers.h > +++ b/drivers/gpu/drm/meson/meson_registers.h > @@ -144,10 +144,15 @@ > #define VIU_SW_RESET_OSD1 BIT(0) > #define VIU_MISC_CTRL0 0x1a06 > #define VIU_CTRL0_VD1_AFBC_MASK 0x170000 > +#define VIU_CTRL0_AFBC_TO_VD1 BIT(20) > #define VIU_MISC_CTRL1 0x1a07 > #define MALI_AFBC_MISC GENMASK(15, 8) > #define D2D3_INTF_LENGTH 0x1a08 > #define D2D3_INTF_CTRL0 0x1a09 > +#define VD1_AFBCD0_MISC_CTRL 0x1a0a > +#define VD1_AXI_SEL_AFB (1 << 12) ---------------------------------------/\ Missing 'C' Thanks Christian for reporting.... last minute checkpatch fix gone wrong. Will fix either in v2 or when applying. Neil > +#define AFBC_VD1_SEL (1 << 10) > +#define VD2_AFBCD1_MISC_CTRL 0x1a0b > #define VIU_OSD1_CTRL_STAT 0x1a10 > #define VIU_OSD1_OSD_BLK_ENABLE BIT(0) > #define VIU_OSD1_OSD_MEM_MODE_LINEAR BIT(2) > @@ -365,6 +370,23 @@ > #define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add > #define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade > #define AFBC_ENABLE 0x1ae0 > +#define AFBC_MODE 0x1ae1 > +#define AFBC_SIZE_IN 0x1ae2 > +#define AFBC_DEC_DEF_COLOR 0x1ae3 > +#define AFBC_CONV_CTRL 0x1ae4 > +#define AFBC_LBUF_DEPTH 0x1ae5 > +#define AFBC_HEAD_BADDR 0x1ae6 > +#define AFBC_BODY_BADDR 0x1ae7 > +#define AFBC_SIZE_OUT 0x1ae8 > +#define AFBC_OUT_YSCOPE 0x1ae9 > +#define AFBC_STAT 0x1aea > +#define AFBC_VD_CFMT_CTRL 0x1aeb > +#define AFBC_VD_CFMT_W 0x1aec > +#define AFBC_MIF_HOR_SCOPE 0x1aed > +#define AFBC_MIF_VER_SCOPE 0x1aee > +#define AFBC_PIXEL_HOR_SCOPE 0x1aef > +#define AFBC_PIXEL_VER_SCOPE 0x1af0 > +#define AFBC_VD_CFMT_H 0x1af1 > > /* vpp */ > #define VPP_DUMMY_DATA 0x1d00 >
diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h index 8ea00546cd4e..f784d7d1fe2e 100644 --- a/drivers/gpu/drm/meson/meson_registers.h +++ b/drivers/gpu/drm/meson/meson_registers.h @@ -144,10 +144,15 @@ #define VIU_SW_RESET_OSD1 BIT(0) #define VIU_MISC_CTRL0 0x1a06 #define VIU_CTRL0_VD1_AFBC_MASK 0x170000 +#define VIU_CTRL0_AFBC_TO_VD1 BIT(20) #define VIU_MISC_CTRL1 0x1a07 #define MALI_AFBC_MISC GENMASK(15, 8) #define D2D3_INTF_LENGTH 0x1a08 #define D2D3_INTF_CTRL0 0x1a09 +#define VD1_AFBCD0_MISC_CTRL 0x1a0a +#define VD1_AXI_SEL_AFB (1 << 12) +#define AFBC_VD1_SEL (1 << 10) +#define VD2_AFBCD1_MISC_CTRL 0x1a0b #define VIU_OSD1_CTRL_STAT 0x1a10 #define VIU_OSD1_OSD_BLK_ENABLE BIT(0) #define VIU_OSD1_OSD_MEM_MODE_LINEAR BIT(2) @@ -365,6 +370,23 @@ #define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add #define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade #define AFBC_ENABLE 0x1ae0 +#define AFBC_MODE 0x1ae1 +#define AFBC_SIZE_IN 0x1ae2 +#define AFBC_DEC_DEF_COLOR 0x1ae3 +#define AFBC_CONV_CTRL 0x1ae4 +#define AFBC_LBUF_DEPTH 0x1ae5 +#define AFBC_HEAD_BADDR 0x1ae6 +#define AFBC_BODY_BADDR 0x1ae7 +#define AFBC_SIZE_OUT 0x1ae8 +#define AFBC_OUT_YSCOPE 0x1ae9 +#define AFBC_STAT 0x1aea +#define AFBC_VD_CFMT_CTRL 0x1aeb +#define AFBC_VD_CFMT_W 0x1aec +#define AFBC_MIF_HOR_SCOPE 0x1aed +#define AFBC_MIF_VER_SCOPE 0x1aee +#define AFBC_PIXEL_HOR_SCOPE 0x1aef +#define AFBC_PIXEL_VER_SCOPE 0x1af0 +#define AFBC_VD_CFMT_H 0x1af1 /* vpp */ #define VPP_DUMMY_DATA 0x1d00
Add the registers of the VPU VD1 Amlogic FBC decoder module, and routing register. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- drivers/gpu/drm/meson/meson_registers.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)