| Message ID | 20200221094531.61894-2-zhiwei_liu@c-sky.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target-riscv: support vector extension part 1 | expand |
On Fri, Feb 21, 2020 at 1:45 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > The 32 vector registers will be viewed as a continuous memory block. > It avoids the convension between element index and (regno, offset). > Thus elements can be directly accessed by offset from the first vector > base address. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index de0a8d893a..2e8d01c155 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -64,6 +64,7 @@ > #define RVA RV('A') > #define RVF RV('F') > #define RVD RV('D') > +#define RVV RV('V') > #define RVC RV('C') > #define RVS RV('S') > #define RVU RV('U') > @@ -93,9 +94,20 @@ typedef struct CPURISCVState CPURISCVState; > > #include "pmp.h" > > +#define RV_VLEN_MAX 512 > + > struct CPURISCVState { > target_ulong gpr[32]; > uint64_t fpr[32]; /* assume both F and D extensions */ > + > + /* vector coprocessor state. */ > + uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); > + target_ulong vxrm; > + target_ulong vxsat; > + target_ulong vl; > + target_ulong vstart; > + target_ulong vtype; > + > target_ulong pc; > target_ulong load_res; > target_ulong load_val; > -- > 2.23.0 >
On 2/21/20 1:45 AM, LIU Zhiwei wrote: > The 32 vector registers will be viewed as a continuous memory block. > It avoids the convension between element index and (regno, offset). > Thus elements can be directly accessed by offset from the first vector > base address. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > --- > target/riscv/cpu.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de0a8d893a..2e8d01c155 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -64,6 +64,7 @@ #define RVA RV('A') #define RVF RV('F') #define RVD RV('D') +#define RVV RV('V') #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') @@ -93,9 +94,20 @@ typedef struct CPURISCVState CPURISCVState; #include "pmp.h" +#define RV_VLEN_MAX 512 + struct CPURISCVState { target_ulong gpr[32]; uint64_t fpr[32]; /* assume both F and D extensions */ + + /* vector coprocessor state. */ + uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); + target_ulong vxrm; + target_ulong vxsat; + target_ulong vl; + target_ulong vstart; + target_ulong vtype; + target_ulong pc; target_ulong load_res; target_ulong load_val;
The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/cpu.h | 12 ++++++++++++ 1 file changed, 12 insertions(+)