| Message ID | 20200222020815.50599-3-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/8] drm/i915/tgl: Extend Wa_1409825376 stepping | expand |
Quoting José Roberto de Souza (2020-02-22 02:08:10) > This will whitelist the HIZ_CHICKEN register so mesa can disable the > optimizations and void hang when using D16_UNORM. But it's not added to the whitelist. -Chris
Ouch! Thanks fixed On Sat, 2020-02-22 at 08:53 +0000, Chris Wilson wrote: > Quoting José Roberto de Souza (2020-02-22 02:08:10) > > This will whitelist the HIZ_CHICKEN register so mesa can disable > > the > > optimizations and void hang when using D16_UNORM. > > But it's not added to the whitelist. > -Chris
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 57a5a39ee902..fbed5bdc9e04 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -598,6 +598,10 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 : FF_MODE2_TDS_TIMER_MASK); + + /* Wa_1806527549:tgl */ + WA_SET_BIT_MASKED(HIZ_CHICKEN, + GEN12_HZ_DEPTH_TEST_LE_GE_OPTIMIZATION_DISABLE); } static void diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cfc238ffd4ae..49872a1dc7a4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7843,6 +7843,7 @@ enum { #define HIZ_CHICKEN _MMIO(0x7018) # define CHV_HZ_8X8_MODE_IN_1X (1 << 15) +# define GEN12_HZ_DEPTH_TEST_LE_GE_OPTIMIZATION_DISABLE (1 << 13) # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3) #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
This will whitelist the HIZ_CHICKEN register so mesa can disable the optimizations and void hang when using D16_UNORM. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Rafael Antognolli <rafael.antognolli@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 5 insertions(+)