@@ -525,6 +525,8 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
state->dpll_set = state->modeset = false;
state->global_state_changed = false;
state->active_pipes = 0;
+ state->ddb_state_changed = false;
+ state->bw_state_changed = false;
}
struct intel_crtc_state *
@@ -468,6 +468,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
if (ret)
return ret;
+ state->bw_state_changed = true;
+
data_rate = intel_bw_data_rate(dev_priv, bw_state);
num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
@@ -15509,8 +15509,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* SKL workaround: bspec recommends we disable the SAGV when we
* have more then one pipe enabled
*/
- if (!intel_can_enable_sagv(state))
- intel_disable_sagv(dev_priv);
+ if (state->bw_state_changed) {
+ if (!intel_can_enable_sagv(state))
+ intel_disable_sagv(dev_priv);
+ }
intel_modeset_verify_disabled(dev_priv, state);
}
@@ -15534,7 +15536,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_encoders_update_prepare(state);
/* Enable all new slices, we might need */
- if (state->modeset)
+ if (state->ddb_state_changed)
icl_dbuf_slice_pre_update(state);
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
@@ -15591,7 +15593,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
/* Disable all slices, we don't need */
- if (state->modeset)
+ if (state->ddb_state_changed)
icl_dbuf_slice_post_update(state);
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
@@ -15610,8 +15612,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_verify_planes(state);
- if (state->modeset && intel_can_enable_sagv(state))
- intel_enable_sagv(dev_priv);
+ if (state->bw_state_changed) {
+ if (intel_can_enable_sagv(state)
+ intel_enable_sagv(dev_priv);
+ }
drm_atomic_helper_commit_hw_done(&state->base);
@@ -471,16 +471,6 @@ struct intel_atomic_state {
bool dpll_set, modeset;
- /*
- * Does this transaction change the pipes that are active? This mask
- * tracks which CRTC's have changed their active state at the end of
- * the transaction (not counting the temporary disable during modesets).
- * This mask should only be non-zero when intel_state->modeset is true,
- * but the converse is not necessarily true; simply changing a mode may
- * not flip the final active status of any CRTC's
- */
- u8 active_pipe_changes;
-
u8 active_pipes;
struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
@@ -494,10 +484,30 @@ struct intel_atomic_state {
bool rps_interactive;
/*
- * active_pipes
+ * active pipes
*/
bool global_state_changed;
+ /*
+ * Does this transaction change the pipes that are active? This mask
+ * tracks which CRTC's have changed their active state at the end of
+ * the transaction (not counting the temporary disable during modesets).
+ * This mask should only be non-zero when intel_state->modeset is true,
+ * but the converse is not necessarily true; simply changing a mode may
+ * not flip the final active status of any CRTC's
+ */
+ u8 active_pipe_changes;
+
+ /*
+ * More granular change indicator for ddb changes
+ */
+ bool ddb_state_changed;
+
+ /*
+ * More granular change indicator for bandwidth state changes
+ */
+ bool bw_state_changed;
+
/* Number of enabled DBuf slices */
u8 enabled_dbuf_slices_mask;
@@ -3894,7 +3894,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
* that changes the active CRTC list or do modeset would need to
* grab _all_ crtc locks, including the one we currently hold.
*/
- if (!intel_state->active_pipe_changes && !intel_state->modeset) {
+ if (!intel_state->ddb_state_changed) {
/*
* alloc may be cleared by clear_intel_crtc_state,
* copy from old state to be sure
@@ -5787,6 +5787,8 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
return PTR_ERR(plane_state);
new_crtc_state->update_planes |= BIT(plane_id);
+
+ state->ddb_state_changed = true;
}
return 0;
The reasoning behind this is such that current dependencies in the code are rather implicit in a sense, we have to constantly check a bunch of different bits like state->modeset, state->active_pipe_changes, which sometimes can indicate counter intuitive changes. By introducing more fine grained state change tracking we achieve better readability and dependency maintenance for the code. For example it is no longer needed to evaluate active_pipe_changes to understand if there were changes for wm/ddb - lets just have a correspondent bit in a state, called ddb_state_changed. active_pipe_changes just indicate whether there was some pipe added or removed. Then we evaluate if wm/ddb had been changed. Same for sagv/bw state. ddb changes may or may not affect if out bandwidth constraints have been changed. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/i915/display/intel_atomic.c | 2 ++ drivers/gpu/drm/i915/display/intel_bw.c | 2 ++ drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++---- .../drm/i915/display/intel_display_types.h | 32 ++++++++++++------- drivers/gpu/drm/i915/intel_pm.c | 4 ++- 5 files changed, 38 insertions(+), 18 deletions(-)