| Message ID | 20200225171125.28885-12-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Proper dbuf global state | expand |
On Tue, 2020-02-25 at 19:11 +0200, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Combine the two per-pipe dbuf debugs into one, and use the canonical > [CRTC:%d:%s] style to identify the crtc. Also use the same style as > the plane code uses for the ddb start/end, and prefix bitmask > properly > with 0x to make it clear they are in fact bitmasks. > > The "how many total slices we are going to use" debug we move to > outside the crtc loop so it gets printed only once at the end. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 26 +++++++++++++++++++------- > 1 file changed, 19 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > b/drivers/gpu/drm/i915/intel_pm.c > index de2822e5c62c..d2edfb820dd9 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3910,10 +3910,6 @@ skl_ddb_get_pipe_allocation_limits(struct > drm_i915_private *dev_priv, > */ > dbuf_slice_mask = skl_compute_dbuf_slices(crtc_state, > active_pipes); > > - DRM_DEBUG_KMS("DBuf slice mask %x pipe %c active pipes %x\n", > - dbuf_slice_mask, > - pipe_name(for_pipe), active_pipes); > - > /* > * Figure out at which DBuf slice we start, i.e if we start at > Dbuf S2 > * and slice size is 1024, the offset would be 1024 > @@ -3996,8 +3992,10 @@ skl_ddb_get_pipe_allocation_limits(struct > drm_i915_private *dev_priv, > alloc->start = offset + start; > alloc->end = offset + end; > > - DRM_DEBUG_KMS("Pipe %d ddb %d-%d\n", for_pipe, > - alloc->start, alloc->end); > + drm_dbg_kms(&dev_priv->drm, > + "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), > active pipes 0x%x\n", > + for_crtc->base.id, for_crtc->name, > + dbuf_slice_mask, alloc->start, alloc->end, > active_pipes); > > return 0; > } > @@ -5457,7 +5455,10 @@ skl_ddb_add_affected_planes(const struct > intel_crtc_state *old_crtc_state, > static int > skl_compute_ddb(struct intel_atomic_state *state) > { > - struct intel_crtc_state *old_crtc_state; > + struct drm_i915_private *dev_priv = to_i915(state->base.dev); > + const struct intel_dbuf_state *old_dbuf_state; > + const struct intel_dbuf_state *new_dbuf_state; > + const struct intel_crtc_state *old_crtc_state; > struct intel_crtc_state *new_crtc_state; > struct intel_crtc *crtc; > int ret, i; > @@ -5474,6 +5475,17 @@ skl_compute_ddb(struct intel_atomic_state > *state) > return ret; > } > > + old_dbuf_state = intel_atomic_get_old_dbuf_state(state); > + new_dbuf_state = intel_atomic_get_new_dbuf_state(state); > + > + if (new_dbuf_state && > + new_dbuf_state->enabled_slices != old_dbuf_state- > >enabled_slices) > + drm_dbg_kms(&dev_priv->drm, > + "Enabled dbuf slices 0x%x -> 0x%x (out of > %d dbuf slices)\n", > + old_dbuf_state->enabled_slices, > + new_dbuf_state->enabled_slices, > + INTEL_INFO(dev_priv)- > >num_supported_dbuf_slices); > + > return 0; > } >
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index de2822e5c62c..d2edfb820dd9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3910,10 +3910,6 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, */ dbuf_slice_mask = skl_compute_dbuf_slices(crtc_state, active_pipes); - DRM_DEBUG_KMS("DBuf slice mask %x pipe %c active pipes %x\n", - dbuf_slice_mask, - pipe_name(for_pipe), active_pipes); - /* * Figure out at which DBuf slice we start, i.e if we start at Dbuf S2 * and slice size is 1024, the offset would be 1024 @@ -3996,8 +3992,10 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, alloc->start = offset + start; alloc->end = offset + end; - DRM_DEBUG_KMS("Pipe %d ddb %d-%d\n", for_pipe, - alloc->start, alloc->end); + drm_dbg_kms(&dev_priv->drm, + "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n", + for_crtc->base.id, for_crtc->name, + dbuf_slice_mask, alloc->start, alloc->end, active_pipes); return 0; } @@ -5457,7 +5455,10 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state, static int skl_compute_ddb(struct intel_atomic_state *state) { - struct intel_crtc_state *old_crtc_state; + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + const struct intel_dbuf_state *old_dbuf_state; + const struct intel_dbuf_state *new_dbuf_state; + const struct intel_crtc_state *old_crtc_state; struct intel_crtc_state *new_crtc_state; struct intel_crtc *crtc; int ret, i; @@ -5474,6 +5475,17 @@ skl_compute_ddb(struct intel_atomic_state *state) return ret; } + old_dbuf_state = intel_atomic_get_old_dbuf_state(state); + new_dbuf_state = intel_atomic_get_new_dbuf_state(state); + + if (new_dbuf_state && + new_dbuf_state->enabled_slices != old_dbuf_state->enabled_slices) + drm_dbg_kms(&dev_priv->drm, + "Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n", + old_dbuf_state->enabled_slices, + new_dbuf_state->enabled_slices, + INTEL_INFO(dev_priv)->num_supported_dbuf_slices); + return 0; }