From patchwork Wed Feb 26 01:46:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11405109 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 625D992A for ; Wed, 26 Feb 2020 01:45:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4AF812082F for ; Wed, 26 Feb 2020 01:45:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4AF812082F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5821B6E094; Wed, 26 Feb 2020 01:45:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id EB64F6E07B for ; Wed, 26 Feb 2020 01:45:21 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Feb 2020 17:45:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,486,1574150400"; d="scan'208";a="438261794" Received: from josouza-mobl2.jf.intel.com (HELO josouza-MOBL2.intel.com) ([10.24.14.234]) by fmsmga006.fm.intel.com with ESMTP; 25 Feb 2020 17:45:21 -0800 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 25 Feb 2020 17:46:03 -0800 Message-Id: <20200226014603.42190-14-jose.souza@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200226014603.42190-1-jose.souza@intel.com> References: <20200226014603.42190-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 14/14] drm/i915/tgl: Implement Wa_1407901919 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This will fix a memory coherence issue. BSpec: 52890 Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++++--------- 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 164b5e82e3e3..b3bb3dd90f02 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -606,6 +606,12 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, IS_TGL_GT_REVID(engine->i915, TGL_GT_REVID_A0, TGL_GT_REVID_A0) ? 0 : FF_MODE2_TDS_TIMER_MASK); + + /* Wa_1407901919:tgl */ + wa_add(wal, ICL_HDC_MODE, HDC_COHERENT_ACCESS_L1_CACHE_DIS | + HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W, 0, + HDC_COHERENT_ACCESS_L1_CACHE_DIS | + HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W); } static void diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e2abd910ae80..3f592636f982 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7892,15 +7892,17 @@ enum { #define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21) /* GEN8 chicken */ -#define HDC_CHICKEN0 _MMIO(0x7300) -#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0) -#define ICL_HDC_MODE _MMIO(0xE5F4) -#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15) -#define HDC_FENCE_DEST_SLM_DISABLE (1 << 14) -#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11) -#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5) -#define HDC_FORCE_NON_COHERENT (1 << 4) -#define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10) +#define HDC_CHICKEN0 _MMIO(0x7300) +#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0) +#define ICL_HDC_MODE _MMIO(0xE5F4) +#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE REG_BIT(15) +#define HDC_FENCE_DEST_SLM_DISABLE REG_BIT(14) +#define HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W REG_BIT(13) +#define HDC_COHERENT_ACCESS_L1_CACHE_DIS REG_BIT(12) +#define HDC_DONOT_FETCH_MEM_WHEN_MASKED REG_BIT(11) +#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT REG_BIT(5) +#define HDC_FORCE_NON_COHERENT REG_BIT(4) +#define HDC_BARRIER_PERFORMANCE_DISABLE REG_BIT(10) #define GEN8_HDC_CHICKEN1 _MMIO(0x7304)