[v2,12/14] drm/i915/tgl: Restrict Wa_1408615072 to GT A0 stepping
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Message ID 20200226014603.42190-12-jose.souza@intel.com
State New
Headers show
Series
  • [v2,01/14] drm/i915/tgl: Split GT and display workarounds
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Commit Message

José Roberto de Souza Feb. 26, 2020, 1:46 a.m. UTC
It is fixed in B0 stepping.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e6d9ec124db8..9df150f877b1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6838,8 +6838,9 @@  static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
 	unsigned int i;
 
 	/* Wa_1408615072:tgl */
-	intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
-			 0, VSUNIT_CLKGATE_DIS_TGL);
+	if (IS_TGL_GT_REVID(dev_priv, TGL_GT_REVID_A0, TGL_GT_REVID_A0))
+		intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
+				 0, VSUNIT_CLKGATE_DIS_TGL);
 
 	/* This is not a WA. Enable VD HCP & MFX_ENC powergate */
 	for (i = 0; i < I915_MAX_VCS; i++) {