diff mbox series

[v2,01/13] arm: dts: calxeda: Basic DT file fixes

Message ID 20200227182210.89512-2-andre.przywara@arm.com (mailing list archive)
State New, archived
Headers show
Series arm: calxeda: update DTS, bindings and MAINTAINERS | expand

Commit Message

Andre Przywara Feb. 27, 2020, 6:21 p.m. UTC
The .dts files for the Calxeda machines are quite old, so carry some
sloppy mistakes that the DT schema checker will complain about.

Fix those issues, they should not have any effect on functionality.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/ecx-2000.dts | 3 ---
 arch/arm/boot/dts/highbank.dts | 7 ++-----
 2 files changed, 2 insertions(+), 8 deletions(-)

Comments

Rob Herring Feb. 27, 2020, 9:42 p.m. UTC | #1
On Thu, Feb 27, 2020 at 06:21:58PM +0000, Andre Przywara wrote:
> The .dts files for the Calxeda machines are quite old, so carry some
> sloppy mistakes that the DT schema checker will complain about.
> 
> Fix those issues, they should not have any effect on functionality.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/boot/dts/ecx-2000.dts | 3 ---
>  arch/arm/boot/dts/highbank.dts | 7 ++-----
>  2 files changed, 2 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
> index 5651ae6dc969..81eb382b4c23 100644
> --- a/arch/arm/boot/dts/ecx-2000.dts
> +++ b/arch/arm/boot/dts/ecx-2000.dts
> @@ -13,7 +13,6 @@
>  	compatible = "calxeda,ecx-2000";
>  	#address-cells = <2>;
>  	#size-cells = <2>;
> -	clock-ranges;
>  
>  	cpus {
>  		#address-cells = <1>;
> @@ -83,8 +82,6 @@
>  		intc: interrupt-controller@fff11000 {
>  			compatible = "arm,cortex-a15-gic";
>  			#interrupt-cells = <3>;
> -			#size-cells = <0>;
> -			#address-cells = <1>;

This is needed if there's an interrupt-map pointing to the gic node. 
However, it should be 0 in that case. 

I thought we had to fix this at some point, but I can't find any record 
of it. So I guess fine to remove. 

Reviewed-by: Rob Herring <robh@kernel.org>

>  			interrupt-controller;
>  			interrupts = <1 9 0xf04>;
>  			reg = <0xfff11000 0x1000>,
> diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
> index f4e4dca6f7e7..9e34d1bd7994 100644
> --- a/arch/arm/boot/dts/highbank.dts
> +++ b/arch/arm/boot/dts/highbank.dts
> @@ -13,7 +13,6 @@
>  	compatible = "calxeda,highbank";
>  	#address-cells = <1>;
>  	#size-cells = <1>;
> -	clock-ranges;
>  
>  	cpus {
>  		#address-cells = <1>;
> @@ -96,7 +95,7 @@
>  		};
>  	};
>  
> -	memory {
> +	memory@0 {
>  		name = "memory";
>  		device_type = "memory";
>  		reg = <0x00000000 0xff900000>;
> @@ -128,14 +127,12 @@
>  		intc: interrupt-controller@fff11000 {
>  			compatible = "arm,cortex-a9-gic";
>  			#interrupt-cells = <3>;
> -			#size-cells = <0>;
> -			#address-cells = <1>;
>  			interrupt-controller;
>  			reg = <0xfff11000 0x1000>,
>  			      <0xfff10100 0x100>;
>  		};
>  
> -		L2: l2-cache {
> +		L2: cache-controller {
>  			compatible = "arm,pl310-cache";
>  			reg = <0xfff12000 0x1000>;
>  			interrupts = <0 70 4>;
> -- 
> 2.17.1
>
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
index 5651ae6dc969..81eb382b4c23 100644
--- a/arch/arm/boot/dts/ecx-2000.dts
+++ b/arch/arm/boot/dts/ecx-2000.dts
@@ -13,7 +13,6 @@ 
 	compatible = "calxeda,ecx-2000";
 	#address-cells = <2>;
 	#size-cells = <2>;
-	clock-ranges;
 
 	cpus {
 		#address-cells = <1>;
@@ -83,8 +82,6 @@ 
 		intc: interrupt-controller@fff11000 {
 			compatible = "arm,cortex-a15-gic";
 			#interrupt-cells = <3>;
-			#size-cells = <0>;
-			#address-cells = <1>;
 			interrupt-controller;
 			interrupts = <1 9 0xf04>;
 			reg = <0xfff11000 0x1000>,
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index f4e4dca6f7e7..9e34d1bd7994 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -13,7 +13,6 @@ 
 	compatible = "calxeda,highbank";
 	#address-cells = <1>;
 	#size-cells = <1>;
-	clock-ranges;
 
 	cpus {
 		#address-cells = <1>;
@@ -96,7 +95,7 @@ 
 		};
 	};
 
-	memory {
+	memory@0 {
 		name = "memory";
 		device_type = "memory";
 		reg = <0x00000000 0xff900000>;
@@ -128,14 +127,12 @@ 
 		intc: interrupt-controller@fff11000 {
 			compatible = "arm,cortex-a9-gic";
 			#interrupt-cells = <3>;
-			#size-cells = <0>;
-			#address-cells = <1>;
 			interrupt-controller;
 			reg = <0xfff11000 0x1000>,
 			      <0xfff10100 0x100>;
 		};
 
-		L2: l2-cache {
+		L2: cache-controller {
 			compatible = "arm,pl310-cache";
 			reg = <0xfff12000 0x1000>;
 			interrupts = <0 70 4>;