[4/4] drm/i915: Implement display w/a 1140 for glk/cnl
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Message ID 20200228203552.30273-4-ville.syrjala@linux.intel.com
State New
Headers show
Series
  • [1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals()
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Commit Message

Ville Syrjälä Feb. 28, 2020, 8:35 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Display w/a #1140 tells us we have to program the transition
watermark to the minimum value on glk/cnl. Let's do that.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f7c11b9f2c29..04013af1eaf1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5116,8 +5116,7 @@  static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
 {
 	struct drm_device *dev = crtc_state->uapi.crtc->dev;
 	const struct drm_i915_private *dev_priv = to_i915(dev);
-	u16 trans_min, trans_y_tile_min;
-	const u16 trans_amount = 10; /* This is configurable amount */
+	u16 trans_min, trans_amount, trans_y_tile_min;
 	u16 wm0_sel_res_b, trans_offset_b, res_blocks;
 
 	/* Transition WM don't make any sense if ipc is disabled */
@@ -5131,9 +5130,16 @@  static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
 	if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
 		return;
 
-	trans_min = 14;
 	if (INTEL_GEN(dev_priv) >= 11)
 		trans_min = 4;
+	else
+		trans_min = 14;
+
+	/* Display WA #1140: glk,cnl */
+	if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+		trans_amount = 0;
+	else
+		trans_amount = 10; /* This is configurable amount */
 
 	trans_offset_b = trans_min + trans_amount;
 
@@ -5160,7 +5166,6 @@  static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
 		/* WA BUG:1938466 add one block for non y-tile planes */
 		if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
 			res_blocks += 1;
-
 	}
 
 	/*