From patchwork Sun Mar 1 11:23:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 11414221 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F358C138D for ; Sun, 1 Mar 2020 11:24:35 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C6B55214DB for ; Sun, 1 Mar 2020 11:24:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="de49N0V6" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C6B55214DB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sntech.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=3JE02FJOO7tqgGf2T/1djhTDWeiXJfV9ZxOO21yZK+I=; b=de49N0V6W8yb6a /RqG9kkgBHb++XimXfztWQ+kdlzUWTFElY+8hTJE+w3alMx416Hcyt82bfzGl+5F5yS4PtEF1GTBh dlWXkXJBp1nDBI4pas9Hxwj4qajSI6zEkwLfuc1Gm/KeHv6KCykQoMHN9wyCMkeE1b0uRAme75hk0 twa9QPpPLS8MoUt8vQCsyE0F08zySCHWtosH/ZYgdndTQbulRthpN9uOlXzmzG7gOKSrmGIraPgex zjeCPOCc309pbqxj9LWYdNodomW6gIJUXHs/6Nhe+s9RxS6iaPld4Z1aTn1JwTQQrq2BuUxXKPYhg VPR/B16KazplrPUnp5iQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1j8Mhq-0007dh-N2; Sun, 01 Mar 2020 11:24:22 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1j8Mhn-0007cq-Ea for linux-rockchip@lists.infradead.org; Sun, 01 Mar 2020 11:24:21 +0000 Received: from p508fc8e5.dip0.t-ipconnect.de ([80.143.200.229] helo=phil.fritz.box) by gloria.sntech.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1j8MhW-0006q0-NX; Sun, 01 Mar 2020 12:24:02 +0100 From: Heiko Stuebner To: jic23@kernel.org Subject: [PATCH] iio: adc: rockchip_saradc: Add support iio buffers Date: Sun, 1 Mar 2020 12:23:53 +0100 Message-Id: <20200301112353.887028-1-heiko@sntech.de> X-Mailer: git-send-email 2.24.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200301_032419_641386_D3A7EDFE X-CRM114-Status: GOOD ( 18.31 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 SPF_NONE SPF: sender does not publish an SPF Record X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lars@metafoo.de, heiko@sntech.de, linux-iio@vger.kernel.org, Heiko Stuebner , linux-kernel@vger.kernel.org, kever.yang@rock-chips.com, linux-rockchip@lists.infradead.org, pmeerw@pmeerw.net, knaack.h@gmx.de, xxm@rock-chips.com Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org From: Simon Xue Add the ability to also support access via (triggered) buffers next to the existing direct mode. Device in question is the Odroid Go Advance that connects a joystick to two of the saradc channels for X and Y axis and the new (and still pending) adc joystick driver of course wants to use triggered buffers from the iio subsystem. Signed-off-by: Simon Xue [some simplifications and added commit description] Signed-off-by: Heiko Stuebner --- drivers/iio/adc/Kconfig | 2 + drivers/iio/adc/rockchip_saradc.c | 137 ++++++++++++++++++++++-------- 2 files changed, 102 insertions(+), 37 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 82e33082958c..55d2499ff757 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -787,6 +787,8 @@ config ROCKCHIP_SARADC tristate "Rockchip SARADC driver" depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST) depends on RESET_CONTROLLER + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER help Say yes here to build support for the SARADC found in SoCs from Rockchip. diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c index 582ba047c4a6..402b2210a682 100644 --- a/drivers/iio/adc/rockchip_saradc.c +++ b/drivers/iio/adc/rockchip_saradc.c @@ -15,7 +15,11 @@ #include #include #include +#include #include +#include +#include +#include #define SARADC_DATA 0x00 @@ -34,7 +38,6 @@ #define SARADC_TIMEOUT msecs_to_jiffies(100) struct rockchip_saradc_data { - int num_bits; const struct iio_chan_spec *channels; int num_channels; unsigned long clk_rate; @@ -49,8 +52,37 @@ struct rockchip_saradc { struct reset_control *reset; const struct rockchip_saradc_data *data; u16 last_val; + const struct iio_chan_spec *last_chan; }; +static void rockchip_saradc_power_down(struct rockchip_saradc *info) +{ + /* Clear irq & power down adc */ + writel_relaxed(0, info->regs + SARADC_CTRL); +} + +static int rockchip_saradc_conversion(struct rockchip_saradc *info, + struct iio_chan_spec const *chan) +{ + reinit_completion(&info->completion); + + /* 8 clock periods as delay between power up and start cmd */ + writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC); + + info->last_chan = chan; + + /* Select the channel to be used and trigger conversion */ + writel(SARADC_CTRL_POWER_CTRL + | (chan->channel & SARADC_CTRL_CHN_MASK) + | SARADC_CTRL_IRQ_ENABLE, + info->regs + SARADC_CTRL); + + if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT)) + return -ETIMEDOUT; + + return 0; +} + static int rockchip_saradc_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -62,24 +94,12 @@ static int rockchip_saradc_read_raw(struct iio_dev *indio_dev, case IIO_CHAN_INFO_RAW: mutex_lock(&indio_dev->mlock); - reinit_completion(&info->completion); - - /* 8 clock periods as delay between power up and start cmd */ - writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC); - - /* Select the channel to be used and trigger conversion */ - writel(SARADC_CTRL_POWER_CTRL - | (chan->channel & SARADC_CTRL_CHN_MASK) - | SARADC_CTRL_IRQ_ENABLE, - info->regs + SARADC_CTRL); - - if (!wait_for_completion_timeout(&info->completion, - SARADC_TIMEOUT)) { - writel_relaxed(0, info->regs + SARADC_CTRL); + ret = rockchip_saradc_conversion(info, chan); + if (ret) { + rockchip_saradc_power_down(info); mutex_unlock(&indio_dev->mlock); - return -ETIMEDOUT; + return ret; } - *val = info->last_val; mutex_unlock(&indio_dev->mlock); return IIO_VAL_INT; @@ -91,7 +111,7 @@ static int rockchip_saradc_read_raw(struct iio_dev *indio_dev, } *val = ret / 1000; - *val2 = info->data->num_bits; + *val2 = chan->scan_type.realbits; return IIO_VAL_FRACTIONAL_LOG2; default: return -EINVAL; @@ -104,10 +124,9 @@ static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id) /* Read value */ info->last_val = readl_relaxed(info->regs + SARADC_DATA); - info->last_val &= GENMASK(info->data->num_bits - 1, 0); + info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0); - /* Clear irq & power down adc */ - writel_relaxed(0, info->regs + SARADC_CTRL); + rockchip_saradc_power_down(info); complete(&info->completion); @@ -118,51 +137,55 @@ static const struct iio_info rockchip_saradc_iio_info = { .read_raw = rockchip_saradc_read_raw, }; -#define ADC_CHANNEL(_index, _id) { \ +#define ADC_CHANNEL(_index, _id, _res) { \ .type = IIO_VOLTAGE, \ .indexed = 1, \ .channel = _index, \ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ .datasheet_name = _id, \ + .scan_index = _index, \ + .scan_type = { \ + .sign = 'u', \ + .realbits = _res, \ + .storagebits = 16, \ + .endianness = IIO_LE, \ + }, \ } static const struct iio_chan_spec rockchip_saradc_iio_channels[] = { - ADC_CHANNEL(0, "adc0"), - ADC_CHANNEL(1, "adc1"), - ADC_CHANNEL(2, "adc2"), + ADC_CHANNEL(0, "adc0", 10), + ADC_CHANNEL(1, "adc1", 10), + ADC_CHANNEL(2, "adc2", 10), }; static const struct rockchip_saradc_data saradc_data = { - .num_bits = 10, .channels = rockchip_saradc_iio_channels, .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels), .clk_rate = 1000000, }; static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = { - ADC_CHANNEL(0, "adc0"), - ADC_CHANNEL(1, "adc1"), + ADC_CHANNEL(0, "adc0", 12), + ADC_CHANNEL(1, "adc1", 12), }; static const struct rockchip_saradc_data rk3066_tsadc_data = { - .num_bits = 12, .channels = rockchip_rk3066_tsadc_iio_channels, .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels), .clk_rate = 50000, }; static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = { - ADC_CHANNEL(0, "adc0"), - ADC_CHANNEL(1, "adc1"), - ADC_CHANNEL(2, "adc2"), - ADC_CHANNEL(3, "adc3"), - ADC_CHANNEL(4, "adc4"), - ADC_CHANNEL(5, "adc5"), + ADC_CHANNEL(0, "adc0", 10), + ADC_CHANNEL(1, "adc1", 10), + ADC_CHANNEL(2, "adc2", 10), + ADC_CHANNEL(3, "adc3", 10), + ADC_CHANNEL(4, "adc4", 10), + ADC_CHANNEL(5, "adc5", 10), }; static const struct rockchip_saradc_data rk3399_saradc_data = { - .num_bits = 10, .channels = rockchip_rk3399_saradc_iio_channels, .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels), .clk_rate = 1000000, @@ -193,6 +216,39 @@ static void rockchip_saradc_reset_controller(struct reset_control *reset) reset_control_deassert(reset); } +static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf = p; + struct iio_dev *i_dev = pf->indio_dev; + struct rockchip_saradc *info = iio_priv(i_dev); + u16 data[20]; + int ret; + int i, j = 0; + + mutex_lock(&i_dev->mlock); + + for_each_set_bit(i, i_dev->active_scan_mask, i_dev->masklength) { + const struct iio_chan_spec *chan = &i_dev->channels[i]; + + ret = rockchip_saradc_conversion(info, chan); + if (ret) { + rockchip_saradc_power_down(info); + goto out; + } + + data[j] = info->last_val; + j++; + } + + iio_push_to_buffers_with_timestamp(i_dev, data, iio_get_time_ns(i_dev)); +out: + mutex_unlock(&i_dev->mlock); + + iio_trigger_notify_done(i_dev->trig); + + return IRQ_HANDLED; +} + static int rockchip_saradc_probe(struct platform_device *pdev) { struct rockchip_saradc *info = NULL; @@ -315,12 +371,19 @@ static int rockchip_saradc_probe(struct platform_device *pdev) indio_dev->channels = info->data->channels; indio_dev->num_channels = info->data->num_channels; - ret = iio_device_register(indio_dev); + ret = iio_triggered_buffer_setup(indio_dev, NULL, + rockchip_saradc_trigger_handler, NULL); if (ret) goto err_clk; + ret = iio_device_register(indio_dev); + if (ret) + goto err_buffer_cleanup; + return 0; +err_buffer_cleanup: + iio_triggered_buffer_cleanup(indio_dev); err_clk: clk_disable_unprepare(info->clk); err_pclk: