diff mbox series

[1/2] x86/mce: add Xeon Icelake to list of CPUs that support PPIN

Message ID c5e5dc42-8037-3774-497e-8bef0edb118d@suse.com (mailing list archive)
State New, archived
Headers show
Series x86/mce: PPIN adjustments coming from Linux | expand

Commit Message

Jan Beulich March 2, 2020, 2:06 p.m. UTC 
From: Tony Luck <tony.luck@intel.com>

New CPU model, same MSRs to control and read the inventory number.

Signed-off-by: Tony Luck <tony.luck@intel.com>
[Linux commit dc6b025de95bcd22ff37c4fabb022ec8a027abf1]
Signed-off-by: Jan Beulich <jbeulich@suse.com>

Comments

Andrew Cooper March 2, 2020, 2:09 p.m. UTC | #1 
On 02/03/2020 14:06, Jan Beulich wrote:
> From: Tony Luck <tony.luck@intel.com>
>
> New CPU model, same MSRs to control and read the inventory number.
>
> Signed-off-by: Tony Luck <tony.luck@intel.com>
> [Linux commit dc6b025de95bcd22ff37c4fabb022ec8a027abf1]
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
diff mbox series

Patch

--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -871,6 +871,7 @@  static void intel_init_ppin(const struct
     case 0x55: /* Skylake X */
     case 0x56: /* Broadwell Xeon D */
     case 0x57: /* Knights Landing */
+    case 0x6a: /* Icelake X */
     case 0x85: /* Knights Mill */
 
         if ( (c != &boot_cpu_data && !ppin_msr) ||