From patchwork Mon Mar 2 14:39:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11415733 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4E490109A for ; Mon, 2 Mar 2020 14:40:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 36194217F4 for ; Mon, 2 Mar 2020 14:40:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 36194217F4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B662F6E46D; Mon, 2 Mar 2020 14:40:07 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 24DC16E46D for ; Mon, 2 Mar 2020 14:40:06 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Mar 2020 06:40:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,507,1574150400"; d="scan'208";a="273742433" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga002.fm.intel.com with SMTP; 02 Mar 2020 06:40:02 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 02 Mar 2020 16:39:59 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Mon, 2 Mar 2020 16:39:43 +0200 Message-Id: <20200302143943.32676-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200302143943.32676-1-ville.syrjala@linux.intel.com> References: <20200302143943.32676-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/selftests: Make the CS timestamp tests work on gen4-snb (sort of) X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä On pre-ivb the CS timestamp register is only present on RCS (despite what snb bspec claims). Let's test it. Also on ctg/elk/ilk the usable part of the timestamp is the UDW so let's read that instead of the LDW. On ctg/elk the 10 msbs of the LDW do actually work, but we configure cs_timestamp_frequency_hz as if they didn't so that we can treat ctg/elk the same as ilk. TODO: figure out why the results we get aren't reliable. On some iterations we can get totally wrong (though consistent) values, on other iterations the values are correct. And somehow changing the offsets into the hwsp also seems to affect the behaviour. Manually reading the register always seems fine, so feels like the problem has something to do with the store rather than the actual register read. Cc: Lionel Landwerlin Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 27 +++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c index f88e445a1cae..f92542e6b5b8 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c @@ -52,7 +52,10 @@ static int write_timestamp(struct i915_request *rq, int slot) if (INTEL_GEN(rq->i915) >= 8) cmd++; *cs++ = cmd; - *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base)); + if (IS_GEN(rq->i915, 5) || IS_G4X(rq->i915)) + *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP_UDW(rq->engine->mmio_base)); + else + *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base)); *cs++ = i915_request_timeline(rq)->hwsp_offset + slot * sizeof(u32); *cs++ = 0; @@ -122,7 +125,8 @@ static int perf_mi_bb_start(void *arg) enum intel_engine_id id; int err = 0; - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */ + /* Do we have any CS_TIMESTAMP? */ + if (INTEL_GEN(gt->i915) < 4) return 0; perf_begin(gt); @@ -132,6 +136,14 @@ static int perf_mi_bb_start(void *arg) u32 cycles[COUNT]; int i; + /* + * Do we have CS_TIMESTAMP for this engine? + * Despite what bspec says SNB does not have this + * for other engines. + */ + if (INTEL_GEN(gt->i915) < 7 && id != RCS0) + continue; + intel_engine_pm_get(engine); batch = create_empty_batch(ce); @@ -246,7 +258,8 @@ static int perf_mi_noop(void *arg) enum intel_engine_id id; int err = 0; - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */ + /* Do we have any CS_TIMESTAMP? */ + if (INTEL_GEN(gt->i915) < 4) return 0; perf_begin(gt); @@ -256,6 +269,14 @@ static int perf_mi_noop(void *arg) u32 cycles[COUNT]; int i; + /* + * Do we have CS_TIMESTAMP for this engine? + * Despite what bspec says SNB does not have this + * for other engines. + */ + if (INTEL_GEN(gt->i915) < 7 && id != RCS0) + continue; + intel_engine_pm_get(engine); base = create_empty_batch(ce);