diff mbox series

[04/33] drm/panel-ilitek-ili9322: Fix dotclocks

Message ID 20200302203452.17977-5-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/panel: Fix dotclocks | expand

Commit Message

Ville Syrjälä March 2, 2020, 8:34 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The currently listed dotclocks disagree with the currently
listed vrefresh rates. Change the dotclocks to match the vrefresh.

Someone tell me which (if either) of the dotclock or vreresh is
correct?

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/panel/panel-ilitek-ili9322.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

Comments

Linus Walleij March 7, 2020, 2:38 p.m. UTC | #1
Hi Ville!

On Mon, Mar 2, 2020 at 9:35 PM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The currently listed dotclocks disagree with the currently
> listed vrefresh rates. Change the dotclocks to match the vrefresh.
>
> Someone tell me which (if either) of the dotclock or vreresh is
> correct?
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

This display is particularly peculiar since it uses
the ITU-T packed streams and like DSI those have
a different clocking than whatever is clocked out to the
actual display by the pixel clock.

Datasheet is here:
https://dflund.se/~triad/krad/dlink-dir-685/ILI9322DS_V1.12.pdf

I see I have consistently set the clocks two orders of
magnitude wrong in this driver, mea culpa :P
But I checked them all and what I think you should
do is just divide them all by 100 and leave as-is.

>  /* Serial RGB modes */
>  static const struct drm_display_mode srgb_320x240_mode = {
> -       .clock = 2453500,
> +       .clock = 14478,

Please set to 24535.

>  static const struct drm_display_mode srgb_360x240_mode = {
> -       .clock = 2700000,
> +       .clock = 10014,

Please set to 27000.

>  /* This is the only mode listed for parallel RGB in the datasheet */
>  static const struct drm_display_mode prgb_320x240_mode = {
> -       .clock = 6400000,
> +       .clock = 6429,

Please set to 64000.

>  static const struct drm_display_mode yuv_640x320_mode = {
> -       .clock = 2454000,
> +       .clock = 18954,

Please set to 24540.

>  static const struct drm_display_mode yuv_720x360_mode = {
> -       .clock = 2700000,
> +       .clock = 22911,

Please set to 27000.

>  /* BT.656 VGA mode, 640x480 */
>  static const struct drm_display_mode itu_r_bt_656_640_mode = {
> -       .clock = 2454000,
> +       .clock = 27480,

Please set to 24540.

>  /* BT.656 D1 mode 720x480 */
>  static const struct drm_display_mode itu_r_bt_656_720_mode = {
> -       .clock = 2700000,
> +       .clock = 29880,

Please set to 27000.

Yours,
Linus Walleij
diff mbox series

Patch

diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9322.c b/drivers/gpu/drm/panel/panel-ilitek-ili9322.c
index f394d53a7da4..5e06e73c2517 100644
--- a/drivers/gpu/drm/panel/panel-ilitek-ili9322.c
+++ b/drivers/gpu/drm/panel/panel-ilitek-ili9322.c
@@ -540,7 +540,7 @@  static int ili9322_enable(struct drm_panel *panel)
 
 /* Serial RGB modes */
 static const struct drm_display_mode srgb_320x240_mode = {
-	.clock = 2453500,
+	.clock = 14478,
 	.hdisplay = 320,
 	.hsync_start = 320 + 359,
 	.hsync_end = 320 + 359 + 1,
@@ -554,7 +554,7 @@  static const struct drm_display_mode srgb_320x240_mode = {
 };
 
 static const struct drm_display_mode srgb_360x240_mode = {
-	.clock = 2700000,
+	.clock = 10014,
 	.hdisplay = 360,
 	.hsync_start = 360 + 35,
 	.hsync_end = 360 + 35 + 1,
@@ -569,7 +569,7 @@  static const struct drm_display_mode srgb_360x240_mode = {
 
 /* This is the only mode listed for parallel RGB in the datasheet */
 static const struct drm_display_mode prgb_320x240_mode = {
-	.clock = 6400000,
+	.clock = 6429,
 	.hdisplay = 320,
 	.hsync_start = 320 + 38,
 	.hsync_end = 320 + 38 + 1,
@@ -584,7 +584,7 @@  static const struct drm_display_mode prgb_320x240_mode = {
 
 /* YUV modes */
 static const struct drm_display_mode yuv_640x320_mode = {
-	.clock = 2454000,
+	.clock = 18954,
 	.hdisplay = 640,
 	.hsync_start = 640 + 252,
 	.hsync_end = 640 + 252 + 1,
@@ -598,7 +598,7 @@  static const struct drm_display_mode yuv_640x320_mode = {
 };
 
 static const struct drm_display_mode yuv_720x360_mode = {
-	.clock = 2700000,
+	.clock = 22911,
 	.hdisplay = 720,
 	.hsync_start = 720 + 252,
 	.hsync_end = 720 + 252 + 1,
@@ -613,7 +613,7 @@  static const struct drm_display_mode yuv_720x360_mode = {
 
 /* BT.656 VGA mode, 640x480 */
 static const struct drm_display_mode itu_r_bt_656_640_mode = {
-	.clock = 2454000,
+	.clock = 27480,
 	.hdisplay = 640,
 	.hsync_start = 640 + 3,
 	.hsync_end = 640 + 3 + 1,
@@ -628,7 +628,7 @@  static const struct drm_display_mode itu_r_bt_656_640_mode = {
 
 /* BT.656 D1 mode 720x480 */
 static const struct drm_display_mode itu_r_bt_656_720_mode = {
-	.clock = 2700000,
+	.clock = 29880,
 	.hdisplay = 720,
 	.hsync_start = 720 + 3,
 	.hsync_end = 720 + 3 + 1,