diff mbox series

x86: refine APIC ID restriction

Message ID 23854915-905d-d564-eca8-10435bd361eb@suse.com (mailing list archive)
State New, archived
Headers show
Series x86: refine APIC ID restriction | expand

Commit Message

Jan Beulich March 3, 2020, 4:17 p.m. UTC 
Now that we distinguish "restricted" and "full" interrupt remapping
mode, the 8-bit-APIC-ID restriction also needs to be enforced for
"restricted".

Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
Obviously to go on top of "AMD/IOMMU: without XT, x2APIC needs to be
forced into physical mode".

Comments

Roger Pau Monne March 3, 2020, 5:15 p.m. UTC | #1 
On Tue, Mar 03, 2020 at 05:17:47PM +0100, Jan Beulich wrote:
> Now that we distinguish "restricted" and "full" interrupt remapping
> mode, the 8-bit-APIC-ID restriction also needs to be enforced for
> "restricted".
> 
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>

Thanks, Roger.
diff mbox series

Patch

--- a/xen/arch/x86/smpboot.c
+++ b/xen/arch/x86/smpboot.c
@@ -1328,7 +1328,7 @@  int __cpu_up(unsigned int cpu)
         return -ENODEV;
 
     if ( (!x2apic_enabled && apicid >= APIC_ALL_CPUS) ||
-         (!iommu_intremap && (apicid >> 8)) )
+         (iommu_intremap != iommu_intremap_full && (apicid >> 8)) )
     {
         printk("Unsupported: APIC ID %#x in xAPIC mode w/o interrupt remapping\n",
                apicid);