drm/i915/gen12: Disable preemption timeout
diff mbox series

Message ID 20200310160047.20748-1-tvrtko.ursulin@linux.intel.com
State New
Headers show
Series
  • drm/i915/gen12: Disable preemption timeout
Related show

Commit Message

Tvrtko Ursulin March 10, 2020, 4 p.m. UTC
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Allow super long OpenCL workloads which cannot be preempted within
the default timeout to run out of the box.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Michal Mrozek <michal.mrozek@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

Comments

Chris Wilson March 10, 2020, 4:06 p.m. UTC | #1
Quoting Tvrtko Ursulin (2020-03-10 16:00:47)
> @@ -316,7 +317,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
>         engine->props.max_busywait_duration_ns =
>                 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT;
>         engine->props.preempt_timeout_ms =
> -               CONFIG_DRM_I915_PREEMPT_TIMEOUT;
> +               INTEL_GEN(i915) == 12 ? 0 : CONFIG_DRM_I915_PREEMPT_TIMEOUT;

Too hidden.

>         engine->props.stop_timeout_ms =
>                 CONFIG_DRM_I915_STOP_TIMEOUT;
>         engine->props.timeslice_duration_ms =
...

+       /* redacted, leaving OpenCL uninterruptible */
+       if (engine->class == RENDER_CLASS && INTEL_GEN(gt->i915) >= 12)
+               engine->props.preempt_timeout_ms = 0;

Please do include a comment for the misbehaviour.
-Chris

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 53ac3f00909a..3dc302038742 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -275,6 +275,7 @@  static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
 {
 	const struct engine_info *info = &intel_engines[id];
+	struct drm_i915_private *i915 = gt->i915;
 	struct intel_engine_cs *engine;
 
 	BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
@@ -301,11 +302,11 @@  static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
 	engine->id = id;
 	engine->legacy_idx = INVALID_ENGINE;
 	engine->mask = BIT(id);
-	engine->i915 = gt->i915;
+	engine->i915 = i915;
 	engine->gt = gt;
 	engine->uncore = gt->uncore;
 	engine->hw_id = engine->guc_id = info->hw_id;
-	engine->mmio_base = __engine_mmio_base(gt->i915, info->mmio_bases);
+	engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
 
 	engine->class = info->class;
 	engine->instance = info->instance;
@@ -316,7 +317,7 @@  static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
 	engine->props.max_busywait_duration_ns =
 		CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT;
 	engine->props.preempt_timeout_ms =
-		CONFIG_DRM_I915_PREEMPT_TIMEOUT;
+		INTEL_GEN(i915) == 12 ? 0 : CONFIG_DRM_I915_PREEMPT_TIMEOUT;
 	engine->props.stop_timeout_ms =
 		CONFIG_DRM_I915_STOP_TIMEOUT;
 	engine->props.timeslice_duration_ms =
@@ -326,7 +327,7 @@  static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
 	if (WARN_ON(engine->context_size > BIT(20)))
 		engine->context_size = 0;
 	if (engine->context_size)
-		DRIVER_CAPS(gt->i915)->has_logical_contexts = true;
+		DRIVER_CAPS(i915)->has_logical_contexts = true;
 
 	/* Nothing to do here, execute in order of dependencies */
 	engine->schedule = NULL;
@@ -342,7 +343,7 @@  static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
 	gt->engine_class[info->class][info->instance] = engine;
 	gt->engine[id] = engine;
 
-	gt->i915->engine[id] = engine;
+	i915->engine[id] = engine;
 
 	return 0;
 }