[PATCHv3,3/5] ARM: dts: exynos: Add FSYS power domain to Exynos542x USB nodes
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Message ID 20200310194854.831-4-linux.amoon@gmail.com
State Changes Requested
Headers show
Series
  • Add support for FSYS power domain and enable suspend clk for Exynos542x SoC
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Commit Message

Anand Moon March 10, 2020, 7:48 p.m. UTC
Add a power domain FSYS for USB 3.0 and USB 2.0 and pdma nodes present
on Exynos542x/5800 SoCs.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
New patch in this series.
---
 arch/arm/boot/dts/exynos5420.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Patch
diff mbox series

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index bd505256a223..4046b669b105 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -396,6 +396,13 @@  msc_pd: power-domain@10044120 {
 			label = "MSC";
 		};
 
+		fsys_pd: power-domain@10044140 {
+			compatible = "samsung,exynos4210-pd";
+			reg = <0x10044140 0x20>;
+			#power-domain-cells = <0>;
+			label = "FSYS";
+		};
+
 		pinctrl_0: pinctrl@13400000 {
 			compatible = "samsung,exynos5420-pinctrl";
 			reg = <0x13400000 0x1000>;
@@ -461,6 +468,7 @@  pdma0: pdma@121a0000 {
 				#dma-cells = <1>;
 				#dma-channels = <8>;
 				#dma-requests = <32>;
+				power-domains = <&fsys_pd>;
 			};
 
 			pdma1: pdma@121b0000 {
@@ -472,6 +480,7 @@  pdma1: pdma@121b0000 {
 				#dma-cells = <1>;
 				#dma-channels = <8>;
 				#dma-requests = <32>;
+				power-domains = <&fsys_pd>;
 			};
 
 			mdma0: mdma@10800000 {
@@ -1374,17 +1383,20 @@  &trng {
 &usbdrd3_0 {
 	clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBD300>;
 	clock-names = "usbdrd30", "usbdrd30_susp_clk";
+	power-domains = <&fsys_pd>;
 };
 
 &usbdrd_phy0 {
 	clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 	clock-names = "phy", "ref";
 	samsung,pmu-syscon = <&pmu_system_controller>;
+	power-domains = <&fsys_pd>;
 };
 
 &usbdrd3_1 {
 	clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBD301>;
 	clock-names = "usbdrd30", "usbdrd30_susp_clk";
+	power-domains = <&fsys_pd>;
 };
 
 &usbdrd_dwc3_1 {
@@ -1395,16 +1407,19 @@  &usbdrd_phy1 {
 	clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
 	clock-names = "phy", "ref";
 	samsung,pmu-syscon = <&pmu_system_controller>;
+	power-domains = <&fsys_pd>;
 };
 
 &usbhost1 {
 	clocks = <&clock CLK_USBH20>;
 	clock-names = "usbhost";
+	power-domains = <&fsys_pd>;
 };
 
 &usbhost2 {
 	clocks = <&clock CLK_USBH20>;
 	clock-names = "usbhost";
+	power-domains = <&fsys_pd>;
 };
 
 &usb2_phy {
@@ -1412,6 +1427,7 @@  &usb2_phy {
 	clock-names = "phy", "ref";
 	samsung,sysreg-phandle = <&sysreg_system_controller>;
 	samsung,pmureg-phandle = <&pmu_system_controller>;
+	power-domains = <&fsys_pd>;
 };
 
 &watchdog {