[PATCHv3,5/5] clk: samsung: exynos542x: Move FSYS subsystem clocks to its sub-CMU
diff mbox series

Message ID 20200310194854.831-6-linux.amoon@gmail.com
State Not Applicable
Headers show
Series
  • Add support for FSYS power domain and enable suspend clk for Exynos542x SoC
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Commit Message

Anand Moon March 10, 2020, 7:48 p.m. UTC
FSYS power domain support usbdrd3, pdma and usb2 power gaiting,
hence move FSYS clk setting to sub-CMU block to support power domain
on/off sequences for device nodes.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
New patch in the series
---
 drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++-------
 1 file changed, 34 insertions(+), 11 deletions(-)

Comments

Krzysztof Kozlowski March 11, 2020, 2:42 p.m. UTC | #1
On Tue, Mar 10, 2020 at 07:48:54PM +0000, Anand Moon wrote:
> FSYS power domain support usbdrd3, pdma and usb2 power gaiting,
> hence move FSYS clk setting to sub-CMU block to support power domain
> on/off sequences for device nodes.
> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> New patch in the series
> ---
>  drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++-------
>  1 file changed, 34 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index c9e5a1fb6653..6c4c47dfcdce 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -859,12 +859,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
>  	DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
>  	DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
>  
> -	/* USB3.0 */
> -	DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
> -	DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
> -	DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
> -	DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),

According to clock diagram these are still in CMU TOP, not FSYS.

> -
>  	/* MMC */
>  	DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
>  	DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
> @@ -1031,8 +1025,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
/>  
>  	/* FSYS Block */
>  	GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
> -	GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
> -	GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
>  	GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
>  	GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
>  	GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
> @@ -1040,9 +1032,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
>  	GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
>  	GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
>  			GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
> -	GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
> -	GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
> -	GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
>  	GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
>  			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
>  
> @@ -1258,6 +1247,28 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
>  	{ DIV2_RATIO0, 0, 0x30 },	/* DIV dout_gscl_blk_300 */
>  };
>  
> +/* USB3.0 */
> +static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = {
> +	DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
> +	DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
> +	DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
> +	DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
> +};
> +
> +static const struct samsung_gate_clock exynos5x_fsys_gate_clks[] __initconst = {
> +	GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
> +	GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
> +	GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
> +	GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
> +	GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
> +};
> +
> +static struct exynos5_subcmu_reg_dump exynos5x_fsys_suspend_regs[] = {
> +	{ GATE_IP_FSYS, 0xffffffff, 0xffffffff }, /* FSYS gates */

This looks wrong. GATE_IP_FSYS has fields also for FSYS2 clocks which
you are not suspending. They do not belong to this CMU.

Don't you need to save also parts of GATE_BUS_FSYS0?

> +	{ SRC_TOP3, 0, BIT(24) },                 /* SW_MUX_PCLK_200_FSYS_SEL */
> +	{ SRC_TOP3, 0, BIT(28) },                 /* SW_MUX_ACLK_200_FSYS_SEL */

Name of clocks from the driver please, not from datasheet. Look at other
examples.

Best regards,
Krzysztof


> +};
> +
>  static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
>  	GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
>  	     CLK_SET_RATE_PARENT, 0),
> @@ -1376,12 +1387,23 @@ static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
>  	.pd_name	= "MAU",
>  };
>  
> +static const struct exynos5_subcmu_info exynos5x_fsys_subcmu = {
> +	.div_clks       = exynos5x_fsys_div_clks,
> +	.nr_div_clks    = ARRAY_SIZE(exynos5x_fsys_div_clks),
> +	.gate_clks	= exynos5x_fsys_gate_clks,
> +	.nr_gate_clks	= ARRAY_SIZE(exynos5x_fsys_gate_clks),
> +	.suspend_regs	= exynos5x_fsys_suspend_regs,
> +	.nr_suspend_regs = ARRAY_SIZE(exynos5x_fsys_suspend_regs),
> +	.pd_name	= "FSYS",
> +};
> +
>  static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
>  	&exynos5x_disp_subcmu,
>  	&exynos5x_gsc_subcmu,
>  	&exynos5x_g3d_subcmu,
>  	&exynos5x_mfc_subcmu,
>  	&exynos5x_mscl_subcmu,
> +	&exynos5x_fsys_subcmu,
>  };
>  
>  static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
> @@ -1391,6 +1413,7 @@ static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
>  	&exynos5x_mfc_subcmu,
>  	&exynos5x_mscl_subcmu,
>  	&exynos5800_mau_subcmu,
> +	&exynos5x_fsys_subcmu,
>  };
>  
>  static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
> -- 
> 2.25.1
>
Anand Moon March 12, 2020, 10:34 a.m. UTC | #2
Hi Krzysztof,

Thanks for your review comments.

On Wed, 11 Mar 2020 at 20:12, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Tue, Mar 10, 2020 at 07:48:54PM +0000, Anand Moon wrote:
> > FSYS power domain support usbdrd3, pdma and usb2 power gaiting,
> > hence move FSYS clk setting to sub-CMU block to support power domain
> > on/off sequences for device nodes.
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > New patch in the series
> > ---
> >  drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++-------
> >  1 file changed, 34 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> > index c9e5a1fb6653..6c4c47dfcdce 100644
> > --- a/drivers/clk/samsung/clk-exynos5420.c
> > +++ b/drivers/clk/samsung/clk-exynos5420.c
> > @@ -859,12 +859,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
> >       DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
> >       DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
> >
> > -     /* USB3.0 */
> > -     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
> > -     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
> > -     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
> > -     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
>
> According to clock diagram these are still in CMU TOP, not FSYS.
>
> > -
> >       /* MMC */
> >       DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
> >       DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
> > @@ -1031,8 +1025,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
> />
> >       /* FSYS Block */
> >       GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
> > -     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
> > -     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
> >       GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
> >       GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
> >       GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
> > @@ -1040,9 +1032,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
> >       GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
> >       GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
> >                       GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
> > -     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
> > -     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
> > -     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
> >       GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
> >                       SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
> >
> > @@ -1258,6 +1247,28 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
> >       { DIV2_RATIO0, 0, 0x30 },       /* DIV dout_gscl_blk_300 */
> >  };
> >
> > +/* USB3.0 */
> > +static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = {
> > +     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
> > +     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
> > +     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
> > +     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
> > +};
> > +
> > +static const struct samsung_gate_clock exynos5x_fsys_gate_clks[] __initconst = {
> > +     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
> > +     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
> > +     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
> > +     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
> > +     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
> > +};
> > +
> > +static struct exynos5_subcmu_reg_dump exynos5x_fsys_suspend_regs[] = {
> > +     { GATE_IP_FSYS, 0xffffffff, 0xffffffff }, /* FSYS gates */
>
> This looks wrong. GATE_IP_FSYS has fields also for FSYS2 clocks which
> you are not suspending. They do not belong to this CMU.
>

Ok. I change the from GATE_IP_FSYS to GATE_BUS_FSYS0 in the above
exynos5x_fsys_gate_clks to make this consistent to used GATE_BUS_FSYS0 for CMU,
with this change it works as per previously.

> Don't you need to save also parts of GATE_BUS_FSYS0?

GATE_BUS_FSYS0 and GATE_IP_FSYS are already part of list
of control register which are saved and restored during suspend and resume
so no point in adding this here, I should drop the GATE_IP_FSYS reg
dump over here.

>
> > +     { SRC_TOP3, 0, BIT(24) },                 /* SW_MUX_PCLK_200_FSYS_SEL */
> > +     { SRC_TOP3, 0, BIT(28) },                 /* SW_MUX_ACLK_200_FSYS_SEL */
>
> Name of clocks from the driver please, not from datasheet. Look at other
> examples.
>

Ok  I will update this as per the examples.

> Best regards,
> Krzysztof
>
>

-Anand

> > +};
> > +
> >  static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
> >       GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
> >            CLK_SET_RATE_PARENT, 0),
> > @@ -1376,12 +1387,23 @@ static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
> >       .pd_name        = "MAU",
> >  };
> >
> > +static const struct exynos5_subcmu_info exynos5x_fsys_subcmu = {
> > +     .div_clks       = exynos5x_fsys_div_clks,
> > +     .nr_div_clks    = ARRAY_SIZE(exynos5x_fsys_div_clks),
> > +     .gate_clks      = exynos5x_fsys_gate_clks,
> > +     .nr_gate_clks   = ARRAY_SIZE(exynos5x_fsys_gate_clks),
> > +     .suspend_regs   = exynos5x_fsys_suspend_regs,
> > +     .nr_suspend_regs = ARRAY_SIZE(exynos5x_fsys_suspend_regs),
> > +     .pd_name        = "FSYS",
> > +};
> > +
> >  static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
> >       &exynos5x_disp_subcmu,
> >       &exynos5x_gsc_subcmu,
> >       &exynos5x_g3d_subcmu,
> >       &exynos5x_mfc_subcmu,
> >       &exynos5x_mscl_subcmu,
> > +     &exynos5x_fsys_subcmu,
> >  };
> >
> >  static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
> > @@ -1391,6 +1413,7 @@ static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
> >       &exynos5x_mfc_subcmu,
> >       &exynos5x_mscl_subcmu,
> >       &exynos5800_mau_subcmu,
> > +     &exynos5x_fsys_subcmu,
> >  };
> >
> >  static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
> > --
> > 2.25.1
> >
Krzysztof Kozlowski March 12, 2020, 11:36 a.m. UTC | #3
On Thu, Mar 12, 2020 at 04:04:57PM +0530, Anand Moon wrote:
> Hi Krzysztof,
> 
> Thanks for your review comments.
> 
> On Wed, 11 Mar 2020 at 20:12, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >
> > On Tue, Mar 10, 2020 at 07:48:54PM +0000, Anand Moon wrote:
> > > FSYS power domain support usbdrd3, pdma and usb2 power gaiting,
> > > hence move FSYS clk setting to sub-CMU block to support power domain
> > > on/off sequences for device nodes.
> > >
> > > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > > ---
> > > New patch in the series
> > > ---
> > >  drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++-------
> > >  1 file changed, 34 insertions(+), 11 deletions(-)
> > >
> > > diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> > > index c9e5a1fb6653..6c4c47dfcdce 100644
> > > --- a/drivers/clk/samsung/clk-exynos5420.c
> > > +++ b/drivers/clk/samsung/clk-exynos5420.c
> > > @@ -859,12 +859,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
> > >       DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
> > >       DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
> > >
> > > -     /* USB3.0 */
> > > -     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
> > > -     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
> > > -     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
> > > -     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
> >
> > According to clock diagram these are still in CMU TOP, not FSYS.
> >
> > > -
> > >       /* MMC */
> > >       DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
> > >       DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
> > > @@ -1031,8 +1025,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
> > />
> > >       /* FSYS Block */
> > >       GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
> > > -     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
> > > -     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
> > >       GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
> > >       GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
> > >       GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
> > > @@ -1040,9 +1032,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
> > >       GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
> > >       GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
> > >                       GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
> > > -     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
> > > -     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
> > > -     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
> > >       GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
> > >                       SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
> > >
> > > @@ -1258,6 +1247,28 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
> > >       { DIV2_RATIO0, 0, 0x30 },       /* DIV dout_gscl_blk_300 */
> > >  };
> > >
> > > +/* USB3.0 */
> > > +static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = {
> > > +     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
> > > +     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
> > > +     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
> > > +     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
> > > +};
> > > +
> > > +static const struct samsung_gate_clock exynos5x_fsys_gate_clks[] __initconst = {
> > > +     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
> > > +     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
> > > +     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
> > > +     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
> > > +     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
> > > +};
> > > +
> > > +static struct exynos5_subcmu_reg_dump exynos5x_fsys_suspend_regs[] = {
> > > +     { GATE_IP_FSYS, 0xffffffff, 0xffffffff }, /* FSYS gates */
> >
> > This looks wrong. GATE_IP_FSYS has fields also for FSYS2 clocks which
> > you are not suspending. They do not belong to this CMU.
> >
> 
> Ok. I change the from GATE_IP_FSYS to GATE_BUS_FSYS0 in the above
> exynos5x_fsys_gate_clks to make this consistent to used GATE_BUS_FSYS0 for CMU,
> with this change it works as per previously.

Wait, you should set here proper registers with proper mask.
> 
> > Don't you need to save also parts of GATE_BUS_FSYS0?
> 
> GATE_BUS_FSYS0 and GATE_IP_FSYS are already part of list
> of control register which are saved and restored during suspend and resume
> so no point in adding this here, I should drop the GATE_IP_FSYS reg
> dump over here.

Since registers are used in separate sub CMU devices, each should
save/restore its part.

Best regards,
Krzysztof
Anand Moon March 12, 2020, 12:54 p.m. UTC | #4
Hi Krzysztof,

On Thu, 12 Mar 2020 at 17:06, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Thu, Mar 12, 2020 at 04:04:57PM +0530, Anand Moon wrote:
> > Hi Krzysztof,
> >
> > Thanks for your review comments.
> >
> > On Wed, 11 Mar 2020 at 20:12, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> > >
> > > On Tue, Mar 10, 2020 at 07:48:54PM +0000, Anand Moon wrote:
> > > > FSYS power domain support usbdrd3, pdma and usb2 power gaiting,
> > > > hence move FSYS clk setting to sub-CMU block to support power domain
> > > > on/off sequences for device nodes.
> > > >
> > > > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > > > ---
> > > > New patch in the series
> > > > ---
> > > >  drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++-------
> > > >  1 file changed, 34 insertions(+), 11 deletions(-)
> > > >
> > > > diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> > > > index c9e5a1fb6653..6c4c47dfcdce 100644
> > > > --- a/drivers/clk/samsung/clk-exynos5420.c
> > > > +++ b/drivers/clk/samsung/clk-exynos5420.c
> > > > @@ -859,12 +859,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
> > > >       DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
> > > >       DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
> > > >
> > > > -     /* USB3.0 */
> > > > -     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
> > > > -     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
> > > > -     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
> > > > -     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
> > >
> > > According to clock diagram these are still in CMU TOP, not FSYS.
> > >
> > > > -
> > > >       /* MMC */
> > > >       DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
> > > >       DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
> > > > @@ -1031,8 +1025,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
> > > />
> > > >       /* FSYS Block */
> > > >       GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
> > > > -     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
> > > > -     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
> > > >       GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
> > > >       GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
> > > >       GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
> > > > @@ -1040,9 +1032,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
> > > >       GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
> > > >       GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
> > > >                       GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
> > > > -     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
> > > > -     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
> > > > -     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
> > > >       GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
> > > >                       SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
> > > >
> > > > @@ -1258,6 +1247,28 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
> > > >       { DIV2_RATIO0, 0, 0x30 },       /* DIV dout_gscl_blk_300 */
> > > >  };
> > > >
> > > > +/* USB3.0 */
> > > > +static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = {
> > > > +     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
> > > > +     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
> > > > +     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
> > > > +     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
> > > > +};
> > > > +
> > > > +static const struct samsung_gate_clock exynos5x_fsys_gate_clks[] __initconst = {
> > > > +     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
> > > > +     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
> > > > +     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
> > > > +     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
> > > > +     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
> > > > +};
> > > > +
> > > > +static struct exynos5_subcmu_reg_dump exynos5x_fsys_suspend_regs[] = {
> > > > +     { GATE_IP_FSYS, 0xffffffff, 0xffffffff }, /* FSYS gates */
> > >
> > > This looks wrong. GATE_IP_FSYS has fields also for FSYS2 clocks which
> > > you are not suspending. They do not belong to this CMU.
> > >
> >
> > Ok. I change the from GATE_IP_FSYS to GATE_BUS_FSYS0 in the above
> > exynos5x_fsys_gate_clks to make this consistent to used GATE_BUS_FSYS0 for CMU,
> > with this change it works as per previously.
>
> Wait, you should set here proper registers with proper mask.

Yes I will set the proper mask for each as per the Exynos 5422 User Manual.

Here is what I feel
CLK_GATE_BUS_FSYS0 controls the PHY clock
CLK_GATE_IP_FSYS controls the IP clock.

So both these field should be part of this FSYS CMU.

> >
> > > Don't you need to save also parts of GATE_BUS_FSYS0?
> >
> > GATE_BUS_FSYS0 and GATE_IP_FSYS are already part of list
> > of control register which are saved and restored during suspend and resume
> > so no point in adding this here, I should drop the GATE_IP_FSYS reg
> > dump over here.
>
> Since registers are used in separate sub CMU devices, each should
> save/restore its part.

Ok I will add both GATE_BUS_FSYS0 and GATE_IP_FSYS
reset value over here.

>
> Best regards,
> Krzysztof
>

-Anand
Anand Moon March 12, 2020, 2:08 p.m. UTC | #5
Hi Krzysztof,

On Thu, 12 Mar 2020 at 18:24, Anand Moon <linux.amoon@gmail.com> wrote:
>
> Hi Krzysztof,
>
> On Thu, 12 Mar 2020 at 17:06, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >
> > On Thu, Mar 12, 2020 at 04:04:57PM +0530, Anand Moon wrote:
> > > Hi Krzysztof,
> > >
> > > Thanks for your review comments.
> > >
> > > On Wed, 11 Mar 2020 at 20:12, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> > > >
> > > > On Tue, Mar 10, 2020 at 07:48:54PM +0000, Anand Moon wrote:
> > > > > FSYS power domain support usbdrd3, pdma and usb2 power gaiting,
> > > > > hence move FSYS clk setting to sub-CMU block to support power domain
> > > > > on/off sequences for device nodes.
> > > > >
> > > > > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > > > > ---
> > > > > New patch in the series
> > > > > ---
> > > > >  drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++-------
> > > > >  1 file changed, 34 insertions(+), 11 deletions(-)
> > > > >
> > > > > diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> > > > > index c9e5a1fb6653..6c4c47dfcdce 100644
> > > > > --- a/drivers/clk/samsung/clk-exynos5420.c
> > > > > +++ b/drivers/clk/samsung/clk-exynos5420.c
> > > > > @@ -859,12 +859,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
> > > > >       DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
> > > > >       DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
> > > > >
> > > > > -     /* USB3.0 */
> > > > > -     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
> > > > > -     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
> > > > > -     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
> > > > > -     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
> > > >
> > > > According to clock diagram these are still in CMU TOP, not FSYS.
> > > >
> > > > > -
> > > > >       /* MMC */
> > > > >       DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
> > > > >       DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
> > > > > @@ -1031,8 +1025,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
> > > > />
> > > > >       /* FSYS Block */
> > > > >       GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
> > > > > -     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
> > > > > -     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
> > > > >       GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
> > > > >       GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
> > > > >       GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
> > > > > @@ -1040,9 +1032,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
> > > > >       GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
> > > > >       GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
> > > > >                       GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
> > > > > -     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
> > > > > -     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
> > > > > -     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
> > > > >       GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
> > > > >                       SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
> > > > >
> > > > > @@ -1258,6 +1247,28 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
> > > > >       { DIV2_RATIO0, 0, 0x30 },       /* DIV dout_gscl_blk_300 */
> > > > >  };
> > > > >
> > > > > +/* USB3.0 */
> > > > > +static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = {
> > > > > +     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
> > > > > +     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
> > > > > +     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
> > > > > +     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
> > > > > +};
> > > > > +
> > > > > +static const struct samsung_gate_clock exynos5x_fsys_gate_clks[] __initconst = {
> > > > > +     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
> > > > > +     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
> > > > > +     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
> > > > > +     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
> > > > > +     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
> > > > > +};
> > > > > +
> > > > > +static struct exynos5_subcmu_reg_dump exynos5x_fsys_suspend_regs[] = {
> > > > > +     { GATE_IP_FSYS, 0xffffffff, 0xffffffff }, /* FSYS gates */
> > > >
> > > > This looks wrong. GATE_IP_FSYS has fields also for FSYS2 clocks which
> > > > you are not suspending. They do not belong to this CMU.
> > > >
> > >
> > > Ok. I change the from GATE_IP_FSYS to GATE_BUS_FSYS0 in the above
> > > exynos5x_fsys_gate_clks to make this consistent to used GATE_BUS_FSYS0 for CMU,
> > > with this change it works as per previously.
> >
> > Wait, you should set here proper registers with proper mask.
>
> Yes I will set the proper mask for each as per the Exynos 5422 User Manual.
>
> Here is what I feel
> CLK_GATE_BUS_FSYS0 controls the PHY clock
> CLK_GATE_IP_FSYS controls the IP clock.
>

Sorry I cannot register both CLK_GATE_BUS_FSYS0 and CLK_GATE_IP_FSYS
to aclk200_fsys, so I got some error like below.

[    0.922693] samsung_clk_register_gate: failed to register clock usbh20
[    0.922857] samsung_clk_register_gate: failed to register clock usbd300
[    0.923000] samsung_clk_register_gate: failed to register clock usbd301

> So both these field should be part of this FSYS CMU.
>
> > >
> > > > Don't you need to save also parts of GATE_BUS_FSYS0?
> > >
> > > GATE_BUS_FSYS0 and GATE_IP_FSYS are already part of list
> > > of control register which are saved and restored during suspend and resume
> > > so no point in adding this here, I should drop the GATE_IP_FSYS reg
> > > dump over here.
> >
> > Since registers are used in separate sub CMU devices, each should
> > save/restore its part.
>
> Ok I will add both GATE_BUS_FSYS0 and GATE_IP_FSYS
> reset value over here.
>

So only changes to this patch is to set the above correctly.

-Anand
Krzysztof Kozlowski March 14, 2020, 5:41 p.m. UTC | #6
On Thu, Mar 12, 2020 at 07:38:30PM +0530, Anand Moon wrote:
> Hi Krzysztof,
> 
> On Thu, 12 Mar 2020 at 18:24, Anand Moon <linux.amoon@gmail.com> wrote:
> >
> > Hi Krzysztof,
> >
> > On Thu, 12 Mar 2020 at 17:06, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> > >
> > > On Thu, Mar 12, 2020 at 04:04:57PM +0530, Anand Moon wrote:
> > > > Hi Krzysztof,
> > > >
> > > > Thanks for your review comments.
> > > >
> > > > On Wed, 11 Mar 2020 at 20:12, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> > > > >
> > > > > On Tue, Mar 10, 2020 at 07:48:54PM +0000, Anand Moon wrote:
> > > > > > FSYS power domain support usbdrd3, pdma and usb2 power gaiting,
> > > > > > hence move FSYS clk setting to sub-CMU block to support power domain
> > > > > > on/off sequences for device nodes.
> > > > > >
> > > > > > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > > > > > ---
> > > > > > New patch in the series
> > > > > > ---
> > > > > >  drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++-------
> > > > > >  1 file changed, 34 insertions(+), 11 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> > > > > > index c9e5a1fb6653..6c4c47dfcdce 100644
> > > > > > --- a/drivers/clk/samsung/clk-exynos5420.c
> > > > > > +++ b/drivers/clk/samsung/clk-exynos5420.c
> > > > > > @@ -859,12 +859,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
> > > > > >       DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
> > > > > >       DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
> > > > > >
> > > > > > -     /* USB3.0 */
> > > > > > -     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
> > > > > > -     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
> > > > > > -     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
> > > > > > -     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
> > > > >
> > > > > According to clock diagram these are still in CMU TOP, not FSYS.
> > > > >
> > > > > > -
> > > > > >       /* MMC */
> > > > > >       DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
> > > > > >       DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
> > > > > > @@ -1031,8 +1025,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
> > > > > />
> > > > > >       /* FSYS Block */
> > > > > >       GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
> > > > > > -     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
> > > > > > -     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
> > > > > >       GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
> > > > > >       GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
> > > > > >       GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
> > > > > > @@ -1040,9 +1032,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
> > > > > >       GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
> > > > > >       GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
> > > > > >                       GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
> > > > > > -     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
> > > > > > -     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
> > > > > > -     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
> > > > > >       GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
> > > > > >                       SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
> > > > > >
> > > > > > @@ -1258,6 +1247,28 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
> > > > > >       { DIV2_RATIO0, 0, 0x30 },       /* DIV dout_gscl_blk_300 */
> > > > > >  };
> > > > > >
> > > > > > +/* USB3.0 */
> > > > > > +static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = {
> > > > > > +     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
> > > > > > +     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
> > > > > > +     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
> > > > > > +     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
> > > > > > +};
> > > > > > +
> > > > > > +static const struct samsung_gate_clock exynos5x_fsys_gate_clks[] __initconst = {
> > > > > > +     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
> > > > > > +     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
> > > > > > +     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
> > > > > > +     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
> > > > > > +     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
> > > > > > +};
> > > > > > +
> > > > > > +static struct exynos5_subcmu_reg_dump exynos5x_fsys_suspend_regs[] = {
> > > > > > +     { GATE_IP_FSYS, 0xffffffff, 0xffffffff }, /* FSYS gates */
> > > > >
> > > > > This looks wrong. GATE_IP_FSYS has fields also for FSYS2 clocks which
> > > > > you are not suspending. They do not belong to this CMU.
> > > > >
> > > >
> > > > Ok. I change the from GATE_IP_FSYS to GATE_BUS_FSYS0 in the above
> > > > exynos5x_fsys_gate_clks to make this consistent to used GATE_BUS_FSYS0 for CMU,
> > > > with this change it works as per previously.
> > >
> > > Wait, you should set here proper registers with proper mask.
> >
> > Yes I will set the proper mask for each as per the Exynos 5422 User Manual.
> >
> > Here is what I feel
> > CLK_GATE_BUS_FSYS0 controls the PHY clock
> > CLK_GATE_IP_FSYS controls the IP clock.
> >
> 
> Sorry I cannot register both CLK_GATE_BUS_FSYS0 and CLK_GATE_IP_FSYS
> to aclk200_fsys, so I got some error like below.
> 
> [    0.922693] samsung_clk_register_gate: failed to register clock usbh20
> [    0.922857] samsung_clk_register_gate: failed to register clock usbd300
> [    0.923000] samsung_clk_register_gate: failed to register clock usbd301
> 
> > So both these field should be part of this FSYS CMU.

I am not sure if I understand your problem. I mentioned that you need
to put proper registers with proper masks into the
exynos5_subcmu_reg_dump. I don't know what have you changed to produce
such error logs.

Best regards,
Krzysztof

Patch
diff mbox series

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index c9e5a1fb6653..6c4c47dfcdce 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -859,12 +859,6 @@  static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
 	DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
 	DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
 
-	/* USB3.0 */
-	DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
-	DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
-	DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
-	DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
-
 	/* MMC */
 	DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
 	DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
@@ -1031,8 +1025,6 @@  static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
 
 	/* FSYS Block */
 	GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
-	GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
-	GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
 	GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
 	GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
 	GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
@@ -1040,9 +1032,6 @@  static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
 	GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
 	GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
 			GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
-	GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
-	GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
-	GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
 	GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
 			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
 
@@ -1258,6 +1247,28 @@  static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
 	{ DIV2_RATIO0, 0, 0x30 },	/* DIV dout_gscl_blk_300 */
 };
 
+/* USB3.0 */
+static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = {
+	DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
+	DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
+	DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
+	DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
+};
+
+static const struct samsung_gate_clock exynos5x_fsys_gate_clks[] __initconst = {
+	GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
+	GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
+	GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
+	GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
+	GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
+};
+
+static struct exynos5_subcmu_reg_dump exynos5x_fsys_suspend_regs[] = {
+	{ GATE_IP_FSYS, 0xffffffff, 0xffffffff }, /* FSYS gates */
+	{ SRC_TOP3, 0, BIT(24) },                 /* SW_MUX_PCLK_200_FSYS_SEL */
+	{ SRC_TOP3, 0, BIT(28) },                 /* SW_MUX_ACLK_200_FSYS_SEL */
+};
+
 static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
 	GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
 	     CLK_SET_RATE_PARENT, 0),
@@ -1376,12 +1387,23 @@  static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
 	.pd_name	= "MAU",
 };
 
+static const struct exynos5_subcmu_info exynos5x_fsys_subcmu = {
+	.div_clks       = exynos5x_fsys_div_clks,
+	.nr_div_clks    = ARRAY_SIZE(exynos5x_fsys_div_clks),
+	.gate_clks	= exynos5x_fsys_gate_clks,
+	.nr_gate_clks	= ARRAY_SIZE(exynos5x_fsys_gate_clks),
+	.suspend_regs	= exynos5x_fsys_suspend_regs,
+	.nr_suspend_regs = ARRAY_SIZE(exynos5x_fsys_suspend_regs),
+	.pd_name	= "FSYS",
+};
+
 static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
 	&exynos5x_disp_subcmu,
 	&exynos5x_gsc_subcmu,
 	&exynos5x_g3d_subcmu,
 	&exynos5x_mfc_subcmu,
 	&exynos5x_mscl_subcmu,
+	&exynos5x_fsys_subcmu,
 };
 
 static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
@@ -1391,6 +1413,7 @@  static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
 	&exynos5x_mfc_subcmu,
 	&exynos5x_mscl_subcmu,
 	&exynos5800_mau_subcmu,
+	&exynos5x_fsys_subcmu,
 };
 
 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {