[12/28] spi: dt-bindings: spi-controller: Slaves have no address cells
diff mbox series

Message ID 20200317093922.20785-13-lkundrak@v3.sk
State New
Headers show
Series
  • DT: Improve validation for Marvell SoCs
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Commit Message

Lubomir Rintel March 17, 2020, 9:39 a.m. UTC
SPI controllers in slave mode have a single child node that has no
address. Enforce #address-cells of zero instead of one.

Fixes: 0a1b929356830 ("spi: Add YAML schemas for the generic SPI options")
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
 .../bindings/spi/spi-controller.yaml          | 23 ++++++++++++++-----
 1 file changed, 17 insertions(+), 6 deletions(-)

Comments

Rob Herring March 19, 2020, 4:51 p.m. UTC | #1
On Tue, Mar 17, 2020 at 3:40 AM Lubomir Rintel <lkundrak@v3.sk> wrote:
>
> SPI controllers in slave mode have a single child node that has no
> address. Enforce #address-cells of zero instead of one.

Geert has fixed this making 'spi-slave' and '#address-cells' mutually exclusive.

https://lore.kernel.org/linux-devicetree/20200306085038.8111-2-geert+renesas@glider.be/

Rob

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/spi/spi-controller.yaml b/Documentation/devicetree/bindings/spi/spi-controller.yaml
index d8e5509a70816..30d774cf6cc95 100644
--- a/Documentation/devicetree/bindings/spi/spi-controller.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml
@@ -15,16 +15,27 @@  description: |
   controller may be described for use in SPI master mode or in SPI slave mode,
   but not for both at the same time.
 
+allOf:
+  - if:
+      required:
+        - spi-slave
+    then:
+      properties:
+        "#address-cells":
+          const: 0
+        "#size-cells":
+          const: 0
+    else:
+      properties:
+        "#address-cells":
+          const: 1
+        "#size-cells":
+          const: 0
+
 properties:
   $nodename:
     pattern: "^spi(@.*|-[0-9a-f])*$"
 
-  "#address-cells":
-    const: 1
-
-  "#size-cells":
-    const: 0
-
   cs-gpios:
     description: |
       GPIOs used as chip selects.