[kvm-unit-tests,v7,06/13] arm/arm64: ITS: Introspection tests

Message ID	20200320092428.20880-7-eric.auger@redhat.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=CcrQ=5F=vger.kernel.org=kvm-owner@kernel.org> From: Eric Auger <eric.auger@redhat.com> To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v7 06/13] arm/arm64: ITS: Introspection tests Date: Fri, 20 Mar 2020 10:24:21 +0100 Message-Id: <20200320092428.20880-7-eric.auger@redhat.com> In-Reply-To: <20200320092428.20880-1-eric.auger@redhat.com> References: <20200320092428.20880-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: kvm-owner@vger.kernel.org Precedence: bulk
Series	arm/arm64: Add ITS tests \| expand [kvm-unit-tests,v7,00/13] arm/arm64: Add ITS tests [kvm-unit-tests,v7,01/13] libcflat: Add other size defines [kvm-unit-tests,v7,02/13] page_alloc: Introduce get_order() [kvm-unit-tests,v7,03/13] arm/arm64: gic: Introduce setup_irq() helper [kvm-unit-tests,v7,04/13] arm/arm64: gicv3: Add some re-distributor defines [kvm-unit-tests,v7,05/13] arm/arm64: gicv3: Set the LPI config and pending tables [kvm-unit-tests,v7,06/13] arm/arm64: ITS: Introspection tests [kvm-unit-tests,v7,07/13] arm/arm64: ITS: its_enable_defaults [kvm-unit-tests,v7,08/13] arm/arm64: ITS: Device and collection Initialization [kvm-unit-tests,v7,09/13] arm/arm64: ITS: Commands [kvm-unit-tests,v7,10/13] arm/arm64: ITS: INT functional tests [kvm-unit-tests,v7,11/13] arm/run: Allow Migration tests [kvm-unit-tests,v7,12/13] arm/arm64: ITS: migration tests [kvm-unit-tests,v7,13/13] arm/arm64: ITS: pending table migration test

diff --git a/arm/Makefile.arm64 b/arm/Makefile.arm64 index 6d3dc2c..60182ae 100644 --- a/arm/Makefile.arm64 +++ b/arm/Makefile.arm64 @@ -19,6 +19,7 @@ endef cstart.o = $(TEST_DIR)/cstart64.o cflatobjs += lib/arm64/processor.o cflatobjs += lib/arm64/spinlock.o +cflatobjs += lib/arm64/gic-v3-its.o OBJDIRS += lib/arm64 diff --git a/arm/gic.c b/arm/gic.c index 2f904b0..649ed81 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -16,6 +16,7 @@ #include <asm/processor.h> #include <asm/delay.h> #include <asm/gic.h> +#include <asm/gic-v3-its.h> #include <asm/smp.h> #include <asm/barrier.h> #include <asm/io.h> @@ -517,6 +518,49 @@ static void gic_test_mmio(void) test_targets(nr_irqs); } +#if defined(__arm__) + +static void test_its_introspection(void) {} + +#else /* __aarch64__ */ + +static void test_its_introspection(void) +{ + struct its_baser *dev_baser = &its_data.device_baser; + struct its_baser *coll_baser = &its_data.coll_baser; + struct its_typer *typer = &its_data.typer; + + if (!gicv3_its_base()) { + report_skip("No ITS, skip ..."); + return; + } + + /* IIDR */ + report(test_readonly_32(gicv3_its_base() + GITS_IIDR, false), + "GITS_IIDR is read-only"), + + /* TYPER */ + report(test_readonly_32(gicv3_its_base() + GITS_TYPER, false), + "GITS_TYPER is read-only"); + + report(typer->phys_lpi, "ITS supports physical LPIs"); + report_info("vLPI support: %s", typer->virt_lpi ? "yes" : "no"); + report_info("ITT entry size = 0x%x", typer->ite_size); + report_info("Bit Count: EventID=%d DeviceId=%d CollId=%d", + typer->eventid_bits, typer->deviceid_bits, + typer->collid_bits); + report(typer->eventid_bits && typer->deviceid_bits && + typer->collid_bits, "ID spaces"); + report_info("Target address format %s", + typer->pta ? "Redist base address" : "PE #"); + + report(dev_baser && coll_baser, "detect device and collection BASER"); + report_info("device table entry_size = 0x%x", dev_baser->esz); + report_info("collection table entry_size = 0x%x", coll_baser->esz); +} + +#endif + int main(int argc, char **argv) { if (!gic_init()) { @@ -548,6 +592,10 @@ int main(int argc, char **argv) report_prefix_push(argv[1]); gic_test_mmio(); report_prefix_pop(); + } else if (strcmp(argv[1], "its-introspection") == 0) { + report_prefix_push(argv[1]); + test_its_introspection(); + report_prefix_pop(); } else { report_abort("Unknown subtest '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 017958d..23d378e 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -122,6 +122,13 @@ smp = $MAX_SMP extra_params = -machine gic-version=3 -append 'active' groups = gic +[its-introspection] +file = gic.flat +smp = $MAX_SMP +extra_params = -machine gic-version=3 -append 'its-introspection' +groups = its +arch = arm64 + # Test PSCI emulation [psci] file = psci.flat diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h new file mode 100644 index 0000000..efd8f67 --- /dev/null +++ b/lib/arm/asm/gic-v3-its.h @@ -0,0 +1,27 @@ +/* + * ITS 32-bit stubs + * + * Copyright (C) 2020, Red Hat Inc, Eric Auger <eric.auger@redhat.com> + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#ifndef _ASMARM_GIC_V3_ITS_H_ +#define _ASMARM_GIC_V3_ITS_H_ + +#ifndef _ASMARM_GIC_H_ +#error Do not directly include <asm/gic-v3-its.h>. Include <asm/gic.h> +#endif + +#include <libcflat.h> + +/* dummy its_data struct to allow gic_get_dt_bases() call */ +struct its_data { + void *base; +}; + +static inline void its_init(void) +{ + assert_msg(false, "not supported on 32-bit"); +} + +#endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index 922cbe9..9564d4f 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -40,6 +40,7 @@ #include <asm/gic-v2.h> #include <asm/gic-v3.h> +#include <asm/gic-v3-its.h> #define PPI(irq) ((irq) + 16) #define SPI(irq) ((irq) + GIC_FIRST_SPI) diff --git a/lib/arm/gic.c b/lib/arm/gic.c index c3c5f6b..a807d5f 100644 --- a/lib/arm/gic.c +++ b/lib/arm/gic.c @@ -9,6 +9,7 @@ struct gicv2_data gicv2_data; struct gicv3_data gicv3_data; +struct its_data its_data; struct gic_common_ops { void (*enable_defaults)(void); @@ -44,12 +45,13 @@ static const struct gic_common_ops gicv3_common_ops = { * Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt */ static bool -gic_get_dt_bases(const char *compatible, void **base1, void **base2) +gic_get_dt_bases(const char *compatible, void **base1, void **base2, void **base3) { struct dt_pbus_reg reg; - struct dt_device gic; + struct dt_device gic, its; struct dt_bus bus; - int node, ret, i; + int node, subnode, ret, i, len; + const void *fdt = dt_fdt(); dt_bus_init_defaults(&bus); dt_device_init(&gic, &bus, NULL); @@ -74,19 +76,39 @@ gic_get_dt_bases(const char *compatible, void **base1, void **base2) base2[i] = ioremap(reg.addr, reg.size); } + if (!base3) { + assert(!strcmp(compatible, "arm,cortex-a15-gic")); + return true; + } + + assert(!strcmp(compatible, "arm,gic-v3")); + + dt_for_each_subnode(node, subnode) { + const struct fdt_property *prop; + + prop = fdt_get_property(fdt, subnode, "compatible", &len); + if (!strcmp((char *)prop->data, "arm,gic-v3-its")) { + dt_device_bind_node(&its, subnode); + ret = dt_pbus_translate(&its, 0, &reg); + assert(ret == 0); + *base3 = ioremap(reg.addr, reg.size); + break; + } + } + return true; } int gicv2_init(void) { return gic_get_dt_bases("arm,cortex-a15-gic", - &gicv2_data.dist_base, &gicv2_data.cpu_base); + &gicv2_data.dist_base, &gicv2_data.cpu_base, NULL); } int gicv3_init(void) { return gic_get_dt_bases("arm,gic-v3", &gicv3_data.dist_base, - &gicv3_data.redist_bases[0]); + &gicv3_data.redist_bases[0], &its_data.base); } int gic_version(void) @@ -100,10 +122,14 @@ int gic_version(void) int gic_init(void) { - if (gicv2_init()) + if (gicv2_init()) { gic_common_ops = &gicv2_common_ops; - else if (gicv3_init()) + } else if (gicv3_init()) { gic_common_ops = &gicv3_common_ops; +#ifdef __aarch64__ + its_init(); +#endif + } return gic_version(); } diff --git a/lib/arm64/asm/gic-v3-its.h b/lib/arm64/asm/gic-v3-its.h new file mode 100644 index 0000000..30f2d90 --- /dev/null +++ b/lib/arm64/asm/gic-v3-its.h @@ -0,0 +1,96 @@ +/* + * All ITS* defines are lifted from include/linux/irqchip/arm-gic-v3.h + * + * Copyright (C) 2020, Red Hat Inc, Eric Auger <eric.auger@redhat.com> + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#ifndef _ASMARM64_GIC_V3_ITS_H_ +#define _ASMARM64_GIC_V3_ITS_H_ + +#ifndef _ASMARM_GIC_H_ +#error Do not directly include <asm/gic-v3-its.h>. Include <asm/gic.h> +#endif + +struct its_typer { + unsigned int ite_size; + unsigned int eventid_bits; + unsigned int deviceid_bits; + unsigned int collid_bits; + bool pta; + bool phys_lpi; + bool virt_lpi; +}; + +struct its_baser { + int index; + size_t psz; + int esz; + bool indirect; + phys_addr_t table_addr; +}; + +#define GITS_BASER_NR_REGS 8 + +struct its_data { + void *base; + struct its_typer typer; + struct its_baser device_baser; + struct its_baser coll_baser; + struct its_cmd_block *cmd_base; + struct its_cmd_block *cmd_write; +}; + +extern struct its_data its_data; + +#define gicv3_its_base() (its_data.base) + +#define GITS_CTLR 0x0000 +#define GITS_IIDR 0x0004 +#define GITS_TYPER 0x0008 +#define GITS_CBASER 0x0080 +#define GITS_CWRITER 0x0088 +#define GITS_CREADR 0x0090 +#define GITS_BASER 0x0100 + +#define GITS_TYPER_PLPIS BIT(0) +#define GITS_TYPER_VLPIS BIT(1) +#define GITS_TYPER_ITT_ENTRY_SIZE GENMASK_ULL(7, 4) +#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 +#define GITS_TYPER_IDBITS GENMASK_ULL(12, 8) +#define GITS_TYPER_IDBITS_SHIFT 8 +#define GITS_TYPER_DEVBITS GENMASK_ULL(17, 13) +#define GITS_TYPER_DEVBITS_SHIFT 13 +#define GITS_TYPER_PTA BIT(19) +#define GITS_TYPER_CIDBITS GENMASK_ULL(35, 32) +#define GITS_TYPER_CIDBITS_SHIFT 32 +#define GITS_TYPER_CIL BIT(36) + +#define GITS_CTLR_ENABLE (1U << 0) + +#define GITS_CBASER_VALID (1UL << 63) + +#define GITS_BASER_VALID BIT(63) +#define GITS_BASER_INDIRECT BIT(62) +#define GITS_BASER_TYPE_SHIFT (56) +#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) +#define GITS_BASER_ENTRY_SIZE_SHIFT (48) +#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1) +#define GITS_BASER_PAGE_SIZE_SHIFT (8) +#define GITS_BASER_PAGE_SIZE_4K (0UL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGES_MAX 256 +#define GITS_BASER_PAGES_SHIFT (0) +#define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1) +#define GITS_BASER_PHYS_ADDR_MASK 0xFFFFFFFFF000 +#define GITS_BASER_TYPE_NONE 0 +#define GITS_BASER_TYPE_DEVICE 1 +#define GITS_BASER_TYPE_COLLECTION 4 + +extern void its_parse_typer(void); +extern void its_init(void); +extern int its_baser_lookup(int i, struct its_baser *baser); + +#endif /* _ASMARM64_GIC_V3_ITS_H_ */ diff --git a/lib/arm64/gic-v3-its.c b/lib/arm64/gic-v3-its.c new file mode 100644 index 0000000..fb8e3f2 --- /dev/null +++ b/lib/arm64/gic-v3-its.c @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2020, Red Hat Inc, Eric Auger <eric.auger@redhat.com> + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#include <asm/gic.h> +#include <alloc_page.h> + +void its_parse_typer(void) +{ + u64 typer = readq(gicv3_its_base() + GITS_TYPER); + struct its_typer *t = &its_data.typer; + + t->ite_size = ((typer & GITS_TYPER_ITT_ENTRY_SIZE) >> GITS_TYPER_ITT_ENTRY_SIZE_SHIFT) + 1; + t->pta = typer & GITS_TYPER_PTA; + t->eventid_bits = ((typer & GITS_TYPER_IDBITS) >> GITS_TYPER_IDBITS_SHIFT) + 1; + t->deviceid_bits = ((typer & GITS_TYPER_DEVBITS) >> GITS_TYPER_DEVBITS_SHIFT) + 1; + + if (typer & GITS_TYPER_CIL) + t->collid_bits = ((typer & GITS_TYPER_CIDBITS) >> GITS_TYPER_CIDBITS_SHIFT) + 1; + else + t->collid_bits = 16; + + t->virt_lpi = typer & GITS_TYPER_VLPIS; + t->phys_lpi = typer & GITS_TYPER_PLPIS; +} + +int its_baser_lookup(int type, struct its_baser *baser) +{ + int i; + + for (i = 0; i < GITS_BASER_NR_REGS; i++) { + void *reg_addr = gicv3_its_base() + GITS_BASER + i * 8; + u64 val = readq(reg_addr); + + if (GITS_BASER_TYPE(val) == type) { + assert((val & GITS_BASER_PAGE_SIZE_MASK) == GITS_BASER_PAGE_SIZE_64K); + baser->esz = GITS_BASER_ENTRY_SIZE(val); + baser->indirect = val & GITS_BASER_INDIRECT; + baser->index = i; + return 0; + } + } + return -1; +} + +/* + * Allocate the BASER table (a single page of size @baser->psz) + * and set the BASER valid + */ +static void its_baser_alloc_table(struct its_baser *baser, size_t size) +{ + unsigned long order = get_order(size >> PAGE_SHIFT); + void *reg_addr = gicv3_its_base() + GITS_BASER + baser->index * 8; + u64 val = readq(reg_addr); + + baser->table_addr = (u64)virt_to_phys(alloc_pages(order)); + + val |= (u64)baser->table_addr | GITS_BASER_VALID; + + writeq(val, reg_addr); +} + +/* + * init_cmd_queue - Allocate the command queue and initialize + * CBASER, CWRITER + */ +static void its_cmd_queue_init(void) +{ + unsigned long order = get_order(SZ_64K >> PAGE_SHIFT); + u64 cbaser; + + its_data.cmd_base = (void *)virt_to_phys(alloc_pages(order)); + + cbaser = ((u64)its_data.cmd_base | (SZ_64K / SZ_4K - 1) | GITS_CBASER_VALID); + + writeq(cbaser, its_data.base + GITS_CBASER); + + its_data.cmd_write = its_data.cmd_base; + writeq(0, its_data.base + GITS_CWRITER); +} + +void its_init(void) +{ + if (!its_data.base) + return; + + its_parse_typer(); + + assert(!its_baser_lookup(GITS_BASER_TYPE_DEVICE, &its_data.device_baser)); + assert(!its_baser_lookup(GITS_BASER_TYPE_COLLECTION, &its_data.coll_baser)); + + its_baser_alloc_table(&its_data.device_baser, SZ_64K); + its_baser_alloc_table(&its_data.coll_baser, SZ_64K); + + its_cmd_queue_init(); +} +

[kvm-unit-tests,v7,06/13] arm/arm64: ITS: Introspection tests

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