| Message ID | 20200320183455.21311-5-ansuelsmth@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/12] pcie: qcom: add missing ipq806x clocks in pcie driver | expand |
On Fri, Mar 20, 2020 at 07:34:47PM +0100, Ansuel Smith wrote: > Add missing ext reset used by ipq806x soc in > pcie qcom driver You say "missing" -- does that mean this is a *new* requirement for this ipq806x device, and previous devices work correctly without this patch? Or does this fix an omission and previous devices actually didn't work correctly? s/soc/SoC/ s/pcie/PCIe/ Period at end of sentence. Please wrap to fill 75 columns.
Hi Ansuel, On Fri, Mar 20, 2020 at 07:34:47PM +0100, Ansuel Smith wrote: > Add missing ext reset used by ipq806x soc in > pcie qcom driver > > Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++++++++++++++++------ > 1 file changed, 18 insertions(+), 6 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 596731b54728..ecc22fd27ea6 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 { > struct reset_control *ahb_reset; > struct reset_control *por_reset; > struct reset_control *phy_reset; > + struct reset_control *ext_reset; > struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; > }; > > @@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) > if (IS_ERR(res->por_reset)) > return PTR_ERR(res->por_reset); > > + res->ext_reset = devm_reset_control_get(dev, "ext"); Please use devm_reset_control_get_exclusive() instead. > + if (IS_ERR(res->ext_reset)) > + return PTR_ERR(res->ext_reset); > + > res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); > return PTR_ERR_OR_ZERO(res->phy_reset); > } > @@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) > reset_control_assert(res->axi_reset); > reset_control_assert(res->ahb_reset); > reset_control_assert(res->por_reset); > + reset_control_assert(res->ext_reset); > reset_control_assert(res->phy_reset); > clk_disable_unprepare(res->iface_clk); > clk_disable_unprepare(res->core_clk); > @@ -301,18 +307,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) > u32 val; > int ret; > > + ret = reset_control_assert(res->ahb_reset); > + if (ret) { > + dev_err(dev, "cannot assert ahb reset\n"); > + return ret; > + } > + > ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); > if (ret < 0) { > dev_err(dev, "cannot enable regulators\n"); > return ret; > } > > - ret = reset_control_assert(res->ahb_reset); > - if (ret) { > - dev_err(dev, "cannot assert ahb reset\n"); > - goto err_assert_ahb; > - } > - This change is not described in the commit message. regards Philipp
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 596731b54728..ecc22fd27ea6 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 { struct reset_control *ahb_reset; struct reset_control *por_reset; struct reset_control *phy_reset; + struct reset_control *ext_reset; struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; }; @@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->por_reset)) return PTR_ERR(res->por_reset); + res->ext_reset = devm_reset_control_get(dev, "ext"); + if (IS_ERR(res->ext_reset)) + return PTR_ERR(res->ext_reset); + res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); return PTR_ERR_OR_ZERO(res->phy_reset); } @@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); + reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); @@ -301,18 +307,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) u32 val; int ret; + ret = reset_control_assert(res->ahb_reset); + if (ret) { + dev_err(dev, "cannot assert ahb reset\n"); + return ret; + } + ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); if (ret < 0) { dev_err(dev, "cannot enable regulators\n"); return ret; } - ret = reset_control_assert(res->ahb_reset); - if (ret) { - dev_err(dev, "cannot assert ahb reset\n"); - goto err_assert_ahb; - } - ret = clk_prepare_enable(res->iface_clk); if (ret) { dev_err(dev, "cannot prepare/enable iface clock\n"); @@ -343,6 +349,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_deassert_ahb; } + ret = reset_control_deassert(res->ext_reset); + if (ret) { + dev_err(dev, "cannot assert ext reset\n"); + goto err_deassert_ahb; + } + /* enable PCIe clocks and resets */ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); val &= ~BIT(0);