[v2,2/2] drm/i915/dp: Attach and set drm connector VRR property
diff mbox series

Message ID 20200325012201.11376-2-manasi.d.navare@intel.com
State New
Headers show
Series
  • [v2,1/2] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
Related show

Commit Message

Navare, Manasi March 25, 2020, 1:22 a.m. UTC
From: Aditya Swarup <aditya.swarup@intel.com>

This function sets the VRR property for connector based
on the platform support, EDID monitor range and DP sink
DPCD capability of outputing video without msa
timing information.

v2:
* Just set this in intel_dp_get_modes instead of new hook (Jani)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

Comments

Navare, Manasi March 31, 2020, 12:26 a.m. UTC | #1
@Jani @Ville, this is the one we had discussed on IRC, could you
take a look at this patch?

Manasi

On Tue, Mar 24, 2020 at 06:22:01PM -0700, Manasi Navare wrote:
> From: Aditya Swarup <aditya.swarup@intel.com>
> 
> This function sets the VRR property for connector based
> on the platform support, EDID monitor range and DP sink
> DPCD capability of outputing video without msa
> timing information.
> 
> v2:
> * Just set this in intel_dp_get_modes instead of new hook (Jani)
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index ef2e06e292d5..95db4e783893 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5843,6 +5843,23 @@ intel_dp_force(struct drm_connector *connector)
>  	intel_display_power_put(dev_priv, aux_domain, wakeref);
>  }
>  
> +static bool intel_dp_is_vrr_capable(struct drm_connector *connector)
> +{
> +	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
> +	const struct drm_display_info *info = &connector->display_info;
> +	struct drm_i915_private *dev_priv = to_i915(connector->dev);
> +
> +	/*
> +	 * DP Sink is capable of Variable refresh video timings if
> +	 * Ignore MSA bit is set in DPCD.
> +	 * EDID monitor range also should be atleast 10 for reasonable
> +	 * Adaptive sync/ VRR end user experience.
> +	 */
> +	return INTEL_GEN(dev_priv) >= 12 &&
> +		drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
> +		info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
> +}
> +
>  static int intel_dp_get_modes(struct drm_connector *connector)
>  {
>  	struct intel_connector *intel_connector = to_intel_connector(connector);
> @@ -5853,6 +5870,10 @@ static int intel_dp_get_modes(struct drm_connector *connector)
>  		int ret = intel_connector_update_modes(connector, edid);
>  		if (ret)
>  			return ret;
> +
> +		if (intel_dp_is_vrr_capable(connector))
> +			drm_connector_set_vrr_capable_property(connector,
> +							       true);
>  	}
>  
>  	/* if eDP has no EDID, fall back to fixed mode */
> @@ -6880,6 +6901,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
>  		connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
>  
>  	}
> +
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		drm_connector_attach_vrr_capable_property(connector);
>  }
>  
>  static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> -- 
> 2.19.1
>

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ef2e06e292d5..95db4e783893 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5843,6 +5843,23 @@  intel_dp_force(struct drm_connector *connector)
 	intel_display_power_put(dev_priv, aux_domain, wakeref);
 }
 
+static bool intel_dp_is_vrr_capable(struct drm_connector *connector)
+{
+	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
+	const struct drm_display_info *info = &connector->display_info;
+	struct drm_i915_private *dev_priv = to_i915(connector->dev);
+
+	/*
+	 * DP Sink is capable of Variable refresh video timings if
+	 * Ignore MSA bit is set in DPCD.
+	 * EDID monitor range also should be atleast 10 for reasonable
+	 * Adaptive sync/ VRR end user experience.
+	 */
+	return INTEL_GEN(dev_priv) >= 12 &&
+		drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
+		info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
+}
+
 static int intel_dp_get_modes(struct drm_connector *connector)
 {
 	struct intel_connector *intel_connector = to_intel_connector(connector);
@@ -5853,6 +5870,10 @@  static int intel_dp_get_modes(struct drm_connector *connector)
 		int ret = intel_connector_update_modes(connector, edid);
 		if (ret)
 			return ret;
+
+		if (intel_dp_is_vrr_capable(connector))
+			drm_connector_set_vrr_capable_property(connector,
+							       true);
 	}
 
 	/* if eDP has no EDID, fall back to fixed mode */
@@ -6880,6 +6901,9 @@  intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
 		connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
 
 	}
+
+	if (INTEL_GEN(dev_priv) >= 12)
+		drm_connector_attach_vrr_capable_property(connector);
 }
 
 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)